- I
- ICCD
- 1995
- 1995 IEEE International Conference on Computer Design (ICCD'95)
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1995 IEEE International Conference on Computer Design (ICCD'95) Austin, Texas October 02-October 04 ISBN: 0-8186-7165-3 Table of Contents
 | Session 1.2.2: Architecture/Algorithms Plenary, Chair: Bing Sheu, University of Southern California, Los Angeles |
B.W. Wah, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Shu Yao, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Ting Yu, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA pp. 4
| Session 1.3.2: System Level Interconnect, Chair: Larry Pileggi, University of Texas at Austin |
J.S.-H. Wang, Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA
W.W.-M. Dai, Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA pp. 18
J. Kudoh, Device Dev. Center, Hitachi Ltd., Tokyo, Japan
T. Takahashi, Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Y. Umada, Device Dev. Center, Hitachi Ltd., Tokyo, Japan
M. Kimura, Device Dev. Center, Hitachi Ltd., Tokyo, Japan
S. Yamamoto, Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Y. Ito, Device Dev. Center, Hitachi Ltd., Tokyo, Japan pp. 25
| Session 1.3.3: Asynchronous Systems, Chair: Steve Nowick, Columbia University |
W.F. Richardson, Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
E. Brunvand, Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA pp. 32
M.R. Greenstreet, Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada pp. 38
K.Y. Yun, Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
D.L. Dill, Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA pp. 44
| Session 1.3.4: Embedded System Analysis, Chair: Sharon Hu, Western Michigan University |
D. Thomas, Carnegie Mellon Univ., Pittsburgh, PA, USA pp. 58
T.Y. Yen, Dept. of Electr. Eng., Princeton Univ., NJ, USA
W. Wolf, Dept. of Electr. Eng., Princeton Univ., NJ, USA pp. 64
| Session 1.4.1: Formal Verification Meets the Real World, Chairs: Mirian Leeser, Cornell University and P.A. Subrahmayam, AT&T Bell Laboratories |
S. Campos, Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
E. Clarke, Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Marrero, Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
M. Minea, Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA pp. 72
A. Kuehlmann, IBM Microelectron. Burlington, Essex Junction, VT, USA pp. 79
A. Chavan, Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Shiu-Kai Chin, Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
S. Ikram, Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Jang Dae Kim, Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Juin-Yeu Zu, Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA pp. 85
| Session 1.4.2: Issues in Superscalar Processors, Chair: Bob Colwell, Intel Corp. |
S. Wallace, Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
N. Dagli, Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
N. Bagherzadeh, Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA pp. 96
T. Hotta, Res. Lab., Hitachi Ltd., Japan pp. 102
J.-D. Wellman, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
E.S. Davidson, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA pp. 110
| Session 1.4.3: SPARC Design Methodologies, Chair: Chin-Long Wey, Michigan State University |
A. Dalal, Sun Microsystems Inc., Mountain View, CA, USA
L. Lev, Sun Microsystems Inc., Mountain View, CA, USA
S. Mitra, Sun Microsystems Inc., Mountain View, CA, USA pp. 118
H. Hao, Sun Microsystems Inc., Mountain View, CA, USA pp. 124
G. Maturana, SPARC Technol., Sun Microsystems Inc., Mountain View, CA, USA
J.L. Ball, SPARC Technol., Sun Microsystems Inc., Mountain View, CA, USA
J. Gee, SPARC Technol., Sun Microsystems Inc., Mountain View, CA, USA
A. Iyer, SPARC Technol., Sun Microsystems Inc., Mountain View, CA, USA
J.M. O'Connor, SPARC Technol., Sun Microsystems Inc., Mountain View, CA, USA pp. 130
| Session 1.4.4: Simulation, Chair: Derek Beatty, Motorola |
A. Devgan, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA pp. 138
J.K. Adams, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.A. Miller, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.E. Thomas, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA pp. 144
J. Kumar, Adv. Design Technol., Motorola Inc., Austin, TX, USA
N. Strader, Adv. Design Technol., Motorola Inc., Austin, TX, USA
J. Freeman, Adv. Design Technol., Motorola Inc., Austin, TX, USA
M. Miller, Adv. Design Technol., Motorola Inc., Austin, TX, USA pp. 150
| Session 2.2.1: Design for Testability, Chair: Sumit Dasgupta, Sematech/IBM Corp. |
J. Carletta, Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
C. Papachristou, Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA pp. 162
Y. Fang, Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Albicki, Dept. of Electr. Eng., Rochester Univ., NY, USA pp. 168
I. Ghosh, Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha, Dept. of Electr. Eng., Princeton Univ., NJ, USA pp. 173
F. Fummi, Dipartimento di Elettronica, Politecnico di Milano, Italy
D. Sciuto, Dipartimento di Elettronica, Politecnico di Milano, Italy
M. Serro, Dipartimento di Elettronica, Politecnico di Milano, Italy pp. 180
| Session 2.2.2: PowerPC(tm), Chair: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola |
R. Evers, Motorola Inc., Austin, TX, USA pp. 188
M.S. Allen, Somerset Design Center, Austin, TX, USA pp. 204
C. Roth, IBM Corp., Austin, TX, USA pp. 212
| Session 2.2.3: Floor Planning & Placement, Chair: Carl Sechen, University of Washington |
Kai-Yuan Chao, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
D.F. Wong, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA pp. 218
G. Holt, Dept. of Comput. Sci., Iowa State Univ., Ames, IA, USA
A. Tyagi, Dept. of Comput. Sci., Iowa State Univ., Ames, IA, USA pp. 224
V. Narayananan, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
D. LaPotin, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R. Gupta, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
G. Vijayan, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA pp. 230
Jin-Tai Yan, Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan pp. 236
| Session 2.2.4: Combinational and Sequential Logic Optimization, Chair: Masahiro Fujita, Fujitsu Labs of America |
T. Kozlowski, Dept. of Electr. & Electron. Eng., Bristol Univ., UK
E.L. Dagless, Dept. of Electr. & Electron. Eng., Bristol Univ., UK
J.M. Saul, Dept. of Electr. & Electron. Eng., Bristol Univ., UK pp. 244
T. Kam, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
T. Villa, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA pp. 250
G. Cabodi, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
S. Quer, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Camurati, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy pp. 258
| Session 2.3.1: Massively Parallel Processing Interconnects, Chair: Joydeep Ghosh, University of Texas at Austin |
P.A. Franaszek, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
C.J. Georgiou, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Chung-Sheng Li, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA pp. 266
G.A. Pratt, Lab. for Comput. Sci., MIT, Cambridge, MA, USA
S.A. Ward, Lab. for Comput. Sci., MIT, Cambridge, MA, USA pp. 271
T. Yokota, Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan
H. Matsuoka, Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan
K. Okamoto, Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan
H. Hirono, Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan
A. Hori, Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan
S. Sakai, Real World Comput. Partnership, Tsukuba Res. Center, Ibaraki, Japan pp. 279
| Session 2.3.2: Test Pattern Generation, Chair: R. Molyneaux |
A.F. Yousif, Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Jun Gu, Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada pp. 286
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA pp. 292
| Session 2.3.3: Caching Strategies, Chair: Jim Bondi, Texas Instruments |
S.J. Walsh, IBM Corp., Research Triangle Park, NC, USA
J.A. Board, IBM Corp., Research Triangle Park, NC, USA pp. 300
R. Yung, Sun Microsystems Labs, Mountain View, CA, USA pp. 307
| Session 2.3.4: Embedded System Architecture & Case Studies, Chair: Jim Browne, University of Texas at Austin |
S.W. Daniel, Real-Time Comput. Lab., Michigan Univ., Ann Arbor, MI, USA
J.L. Rexford, Real-Time Comput. Lab., Michigan Univ., Ann Arbor, MI, USA
J.W. Dolter, Real-Time Comput. Lab., Michigan Univ., Ann Arbor, MI, USA
K.G. Shin, Real-Time Comput. Lab., Michigan Univ., Ann Arbor, MI, USA pp. 320
J.-P. Theis, Applied Microelectron. Lab., Public Res Centre Henri Tudor, Luxembourg City, Luxembourg
L. Thiele, Applied Microelectron. Lab., Public Res Centre Henri Tudor, Luxembourg City, Luxembourg pp. 326
A. Wolfe, Dept. of Electr. Eng., Princeton Univ., NJ, USA pp. 332
| Session 2.4.1: ATM and High-Speed Networking Alternatives, Chair: Bob Horst, Tandem Computer |
Jin Li, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Chuan-Lin Wu, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA pp. 340
V. Kotov, Hewlett-Packard Co., Palo Alto, CA, USA
T. Rokicki, Hewlett-Packard Co., Palo Alto, CA, USA pp. 346
S.E. Butner, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
D.A. Skirmont, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA pp. 352
| Session 2.4.2: Routing & Extraction, Chair: Lukas van Ginneken, Synopsys, Inc. |
F. Beeftink, Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands pp. 360
Jin-Tai Yan, Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan pp. 366
Yao-Wen Chang, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
C.K. Wong, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA pp. 372
| Session 2.4.3: Asynchronous Datapaths, Chair: Erik Brunvand, University of Utah |
B. Stott, Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
D. Johnson, Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
V. Akella, Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA pp. 380
Chin-Long Wey, Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Haiyan Wang, Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Cheng-Ping Wang, Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA pp. 386
| Session 2.4.4: FPGA - Synthesis, Chair: Steve Trimberger, Xilinx |
Yao-Wen Chang, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
C.K. Wong, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA pp. 394
S. Thakur, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA pp. 402
Aigo Lu, Dept. of Electr. & Electron. Eng., Bristol Univ., UK
E. Dagless, Dept. of Electr. & Electron. Eng., Bristol Univ., UK
J. Saul, Dept. of Electr. & Electron. Eng., Bristol Univ., UK pp. 409
R. Murgai, Fujitsu Labs of America Inc., San Jose, CA, USA
M. Fujita, Fujitsu Labs of America Inc., San Jose, CA, USA
F. Hirose, Fujitsu Labs of America Inc., San Jose, CA, USA pp. 415
| Session 3.1.1: Design & Test Plenary, Chair: Alexander Albicki, University of Rochester |
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA pp. 426
| Session 3.1.2: CAD Plenary, Chair: Luc Claesen, IMEC |
B.J. Hosticka, Fraunhofer Inst. of Microelectron. Circuits & Syst., Duisberg, Germany pp. 428
| Session 3.2.1: Topics in High-Level Synthesis, Chair: Ahmed Jerraya, TIMA/INPG |
I.P. Radivojevic, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
F. Brewer, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA pp. 434
N.L. Passes, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
E.H.-M. Sha, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA pp. 440
S. Katkoori, Dept. of ECE&CS, Cincinnati Univ., OH, USA
N. Kumar, Dept. of ECE&CS, Cincinnati Univ., OH, USA
R. Vemuri, Dept. of ECE&CS, Cincinnati Univ., OH, USA pp. 446
| Session 3.2.2: Low Power and High-Performance Circuits, Chair: Kit Cham, Hewlett-Packard |
Chuan-Yu Wang, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA pp. 454
K. Srivatsan, Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
C. Chakrabarti, Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
L. Lucke, Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA pp. 460
H. Yamada, Res. Lab., Hitachi Ltd., Kanagawa, Japan
T. Hotta, Res. Lab., Hitachi Ltd., Kanagawa, Japan pp. 466
| Session 3.2.3: Arithmetic Modules, Chair: N. Ranganathan, University of South Florida |
Tzu-Hsi Pan, Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Hyon-Sok Kay, Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Youngsun Chun, Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Chin-Long Wey, Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA pp. 479
M.J. Schulte, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA pp. 686
| Session 3.2.4: Architectures for Signal Processors, Chair: Kaushik Roy, Purdue University |
A. Tsutsui, NTT Opt. Network Syst. Labs., Kanagawa, Japan
T. Miyazaki, NTT Opt. Network Syst. Labs., Kanagawa, Japan
K. Yamada, NTT Opt. Network Syst. Labs., Kanagawa, Japan
N. Ohta, NTT Opt. Network Syst. Labs., Kanagawa, Japan pp. 486
E.Y. Chou, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
B.J. Sheu, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
T.H. Wu, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
R.C. Chang, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA pp. 492
S. Dutta, Dept. of Electr. Eng., Princeton Univ., NJ, USA
W. Wolf, Dept. of Electr. Eng., Princeton Univ., NJ, USA
A. Wolfe, Dept. of Electr. Eng., Princeton Univ., NJ, USA pp. 498
| Session 3.3.1: Memory System Performance, Chair: Pradip Bose, IBM T.J. Watson Research Center |
D.J. Lilja, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA pp. 506
Chi-Hung Chi, Dept. of Comput. Sci., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Siu-Chung Lau, Dept. of Comput. Sci., Chinese Univ. of Hong Kong, Shatin, Hong Kong pp. 512
| Session 3.3.2: Emerging Technologies for Processor Verification, Chair: Warren Hunt, Computational Logic, Inc. |
M. Leeser, Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
J. O'Leary, Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA pp. 526
Y.V. Hoskote, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
D. Moundanos, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J.A. Abraham, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA pp. 532
D.A. Cyrluk, Dept. of Comput. Sci., Stanford Univ., CA, USA
M.K. Srivas, Dept. of Comput. Sci., Stanford Univ., CA, USA pp. 538
| Session 3.3.3: Memory Architectures for Signal Processing, Chair: Bryan Ackland, AT&T Bell Laboratories |
M.C. Herbordt, Dept. of Electr. & Comput. Eng., Houston Univ., TX, USA
C.C. Weems, Dept. of Electr. & Comput. Eng., Houston Univ., TX, USA pp. 546
E. de Greef, VLSI Syst. Design Group, IMEC, Leuven, Belgium
F. Catthoor, VLSI Syst. Design Group, IMEC, Leuven, Belgium
H. De Man, VLSI Syst. Design Group, IMEC, Leuven, Belgium pp. 552
S. Iwasa, Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
Shung Ho Shing, Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
H. Mogi, Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
H. Nozuwe, Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
H. Hayashi, Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
O. Wakamori, Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
T. Ohmizo, Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
K. Tanaka, Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
H. Sakai, Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
M. Saito, Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan pp. 558
| Session 3.3.4: Novel Design Concepts, Chair: Christos Papachristou, Case Western Reserve University |
A. Albicki, Dept. of Electr. Eng., Rochester Univ., NY, USA pp. 566
A.M. Tokarnia, Fac. de Engenharia Eletrica, Univ. Estadual de Campinas, Sao Paulo, Brazil
A.M. Peterson, Fac. de Engenharia Eletrica, Univ. Estadual de Campinas, Sao Paulo, Brazil pp. 571
Tan-Li Chou, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA pp. 577
| Session 3.4.1: FSM Verification, Chair: Gabriel Bischoff, Digital Equipment Corporation |
A.J. Daga, Interconnectix Inc., Portland, OR, USA pp. 584
G.M. Swamy, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
V. Singhal, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA pp. 590
M. Pandey, Carnegie Mellon Univ., Pittsburgh, PA, USA
A. Jain, Carnegie Mellon Univ., Pittsburgh, PA, USA
R.E. Bryant, Carnegie Mellon Univ., Pittsburgh, PA, USA
D. Beatty, Carnegie Mellon Univ., Pittsburgh, PA, USA
G. York, Carnegie Mellon Univ., Pittsburgh, PA, USA
S. Jain, Carnegie Mellon Univ., Pittsburgh, PA, USA pp. 596
R. Drechsler, Dept. of Comput. Sci., Frankfurt Univ., Germany
B. Becker, Dept. of Comput. Sci., Frankfurt Univ., Germany pp. 602
| Session 3.4.2: Fault Simulation, Chair: Srimat Chakradhar, NEC |
M.B. Amin, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
B. Vinnakota, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA pp. 610
S. Parkes, Sierra Vista Res. Inc., Los Gatos, CA, USA
P. Banerjee, Sierra Vista Res. Inc., Los Gatos, CA, USA
J. Patel, Sierra Vista Res. Inc., Los Gatos, CA, USA pp. 616
B. Grayson, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
S.A. Shaikh, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
S.A. Szygenda, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA pp. 622
M.S. Hsiao, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA pp. 628
| Session 3.4.3: Application-Specific Processors, Chair: Ashwiai Nanda, Texas Instruments |
R.K. Krishnamurthy, Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
R. Sridhar, Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA pp. 638
Hyesook Lim, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA pp. 644
A. Ejnioui, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
N. Ranganathan, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA pp. 650
Wai-Chi Fang, Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
B.J. Sheu, Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
H. Venus, Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
R. Sandau, Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA pp. 703
| Session 3.4.4: Performance Driven Synthesis, Chair: Andreas Kuehlmann, IBM T.J. Watson Research Center |
H. Vaishnav, Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram, Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA pp. 658
J. Shinn-Hwa Wang, Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA
W. Wei-Ming Dai, Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA pp. 664
M. Fujita, Fujitsu Labs. of America Inc., San Jose, CA, USA pp. 671
Hong-Yean Hsieh, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Wentai Liu, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
R.K. Cavin, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
C.T. Gray, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA pp. 680 Usage of this product signifies your acceptance of the Terms of Use.
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