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  • 2005 International Conference on Computer Aided Design (ICCAD'05)
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2005 International Conference on Computer Aided Design (ICCAD'05)
San Jose, CA, USA
May 31-May 31
ISBN: 0-7803-9254-X
Table of Contents
Introduction
Session 1A - Memory and arithmetic optimizations
Wenrui Gong, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Gang Wang, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
R. Kastner, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 3-6
R. Ruiz-Sautua, Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
M.C. Molina, Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
J.M. Mendias, Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
R. Hermida, Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
pp. 7-12
P. Flores, IST-INESC-ID, Lisboa, Portugal
J. Monteiro, IST-INESC-ID, Lisboa, Portugal
E. Costa, Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
pp. 13-16
Session 1B - Design manufacturing interaction
Ho-Yan Wong, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Lerong Cheng, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Yan Lin, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Lei He, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 19-24
Y. Ran, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Marek-Sadowska, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 25-32
Session 1C - Detailed placement
T. Luo, Dept. of ECE, Texas Univ. at Austin, TX, USA
H. Ren, Dept. of ECE, Texas Univ. at Austin, TX, USA
C.J. Alpert, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
D.Z. Pan, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 41-47
Min Pan, Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
N. Viswanathan, Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
C. Chu, Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 48-55
Kai-hui Chang, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
I.L. Markov, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
V. Bertacco, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 56-63
Xin Hao, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
F. Brewer, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 64-70
Session 1D - Digital, analog and RF test
M.C.-T. Chao, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, Santa Barbara, CA, USA
Seongmoon Wang, Duke Univ., Durham, NC, USA
S.T. Chakradhar, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Kwang-Ting Cheng, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 80-87
A. Sehgal, Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
K. Chakrabarty, Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 88-93
K. Chakrabarty, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin Chu, Taiwan
K. Chakrabarty, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin Chu, Taiwan
J.E. Chen, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin Chu, Taiwan
pp. 94-99
D. Bordoley, Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
H. Nguyen, Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
M. Soma, Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 100-107
Session 2A - Embedded turorial: design trends
O. Takahashi, IBM Syst. & Technol. Group, Austin, TX, USA
R. Cook, IBM Syst. & Technol. Group, Austin, TX, USA
S. Cottier, IBM Syst. & Technol. Group, Austin, TX, USA
S.H. Dhong, IBM Syst. & Technol. Group, Austin, TX, USA
B. Flachs, IBM Syst. & Technol. Group, Austin, TX, USA
pp. 111-117
R.B. Staszewski, Wireless Analog Technol. Center, Texas Instruments Inc., Dallas, TX, USA
K. Muhammad, Wireless Analog Technol. Center, Texas Instruments Inc., Dallas, TX, USA
D. Leipold, Wireless Analog Technol. Center, Texas Instruments Inc., Dallas, TX, USA
pp. 122-129
Session 2B - Physical design for manufacturing
Jianfeng Luo, Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
Qing Su, Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
C. Chiang, Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
J. Kawa, Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
pp. 133-140
J.D. Ma, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., New York, NY, USA
C.F. Fang, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., New York, NY, USA
R.A. Rutenbar, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., New York, NY, USA
Xiaolin Xie, Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
D.S. Boning, IBM Syst. & Technol. Group, Austin, TX, USA
pp. 141-148
C. Chiang, Adv. Technol. Group, Synopsys, Mountain View, CA, USA
A.B. Kahng, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., New York, NY, USA
S. Sinha, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., New York, NY, USA
X. Xu, Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
pp. 149-156
Session 2C - Large-scale layout techniques
Tung-Chieh Chen, Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
Yao-Wen Chang, Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
Shyh-Chang Lin, Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
pp. 159-164
J. Cong, Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
M. Romesis, Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
J.R. Shinnerl, Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
pp. 165-172
A.B. Kahng, Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
S. Reda, Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
pp. 173-180
Session 2D - Novel ideas and logic synthesis
Yinghua Li, California Univ., Berkeley, CA, USA
A. Kondratyev, Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
R. Brayton, Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
pp. 183-188
Chuan Lin, Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Jia Wang, Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Hai Zhou, Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 189-195
Sanghamitra Roy, Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
Weijen Chen, Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
Weijen Chen, Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
pp. 196-203
Session 3A - Embedded tutorial: opportunities and challenges with double-gated devices
Tsu-Jae King, Adv. Technol. Group, Synopsys, Inc., Mountain View, CA, USA
pp. 207-210
V.P. Trivedi, Freescale Semicond., Austin, TX, USA
G. Fossum, Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
L. Mathew, Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
M.M. Chowdhury, Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
W. Zhang, IBM Syst. & Technol. Group, Austin, TX, USA
pp. 211-216
K. Roy, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
H. Mahmoodi, Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
S. Mukhopadhyay, Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
H. Ananthan, Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
A. Bansal, IBM Syst. & Technol. Group, Austin, TX, USA
pp. 217-224
J. Rowlette, Dept. of Electr. & Mech. Eng., Stanford Univ., CA, USA
E. Pop, Dept. of Electr. & Mech. Eng., Stanford Univ., CA, USA
S. Sinha, Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
M. Panzer, Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
K. Goodson, IBM Syst. & Technol. Group, Austin, TX, USA
pp. 225-228
Session 3B - Routing and application specific NoC architectures
K. Srinivasan, Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
K.S. Chatha, Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
G. Konjevod, Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
pp. 231-237
M.K.F. Schafer, Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
T. Hollstein, Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
H. Zimmer, Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner, Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 238-245
U.Y. Ogras, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Marculescu, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 246-253
J. Chan, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
S. Parameswaran, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 254-259
Session 3C - Memory driven code and architecture optimizations
J. Cong, Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
Guoling Han, Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
Zhiru Zhang, Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
pp. 263-270
G. Chen, Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir, Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA, USA
pp. 271-274
M. Kandemir, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 275-278
Guilin Chen, Pennsylvania State Univ., University Park, PA, USA
O. Ozturk, Pennsylvania State Univ., University Park, PA, USA
M. Kandemir, Pennsylvania State Univ., University Park, PA, USA
I. Kolcu, Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 279-282
Session 3D - Exploiting arithmetic constructs in verification
T. Raudvere, R. Inst. of Technol., Stockholm, Sweden
A.K. Singh, R. Inst. of Technol., Stockholm, Sweden
I. Sander, R. Inst. of Technol., Stockholm, Sweden
A. Jantsch, R. Inst. of Technol., Stockholm, Sweden
pp. 285-290
N. Shekhar, Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake, UT, USA
P. Kalla, Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake, UT, USA
F. Enescu, R. Inst. of Technol., Stockholm, Sweden
S. Gopalakrishnan, R. Inst. of Technol., Stockholm, Sweden
pp. 291-296
G. Parthasarathy, California Univ., Santa Barbara, CA, USA
M.K. Iyer, California Univ., Santa Barbara, CA, USA
K.-T. Cheng, California Univ., Santa Barbara, CA, USA
F. Brewer, California Univ., Santa Barbara, CA, USA
pp. 297-302
Guilin Chen, Pennsylvania State Univ., University Park, PA, USA
Mahmut Kandemir, Pennsylvania State Univ., University Park, PA, USA
pp. 303-306
Session 4A - Buffers and voltage islands
Huaizhi Wu, Cadence Design Syst., Inc., San Jose, CA, USA
I-Min Liu, Pennsylvania State Univ., University Park, PA, USA
M.D.F. Wong, California Univ., Santa Barbara, CA, USA
Yusu Wang, California Univ., Santa Barbara, CA, USA
pp. 309-316
Liang Deng, Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
M.D.F. Wong, Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 317-321
Ruiming Chen, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Hai Zhou, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 322-326
Session 4B - Sequential circuit optimization
Chuan Lin, Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Hai Zhou, Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 329-334
Hyeonmin Lim, Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
Kyungsoo Lee, Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
Youngjin Cho, Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
Naehyuck Chang, Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
pp. 335-342
A. Gupta, Tabula, Inc., Santa Clara, CA, USA
C. Selvidge, Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
pp. 343-347
Session 4C - Power grid verification
Yu Zhong, Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
M.D.F. Wong, Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 351-357
D. Kouroussis, Dept. of Electr. & Comput. Eng.,, Toronto Univ., Ont., Canada
I.A. Ferzli, Dept. of Electr. & Comput. Eng.,, Toronto Univ., Ont., Canada
F.N. Najm, Dept. of Electr. & Comput. Eng.,, Toronto Univ., Ont., Canada
pp. 358-364
Sanjay Pant, Michigan Univ., Ann Arbor, MI, USA
D. Blaauw, Michigan Univ., Ann Arbor, MI, USA
pp. 365-371
Session 4D - Nanoelectronics
A. DeHon, Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA
K.K. Likharev, Michigan Univ., Ann Arbor, MI, USA
pp. 375-382
N. Srivastava, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
K. Banerjee, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 383-390
Session 5A - Variability in design
Di Wu, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
G. Venkataraman, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Jiang Hu, Dept. of Electr. & Comput. Eng.,, Toronto Univ., Ont., Canada
Quiyang Li, Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
R. Mahapatra, IBM Syst. & Technol. Group, Austin, TX, USA
pp. 393-397
Y. Tsukamoto, Renesas Technol. Corp., Itami, Japan
K. Nii, Renesas Technol. Corp., Itami, Japan
S. Imaoka, Dept. of Electr. & Comput. Eng.,, Toronto Univ., Ont., Canada
Y. Oda, Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
S. Ohbayashi, IBM Syst. & Technol. Group, Austin, TX, USA
pp. 398-405
Suwen Yang, Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
M. Greenstreet, Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 406-412
Session 5B - Efficient analog design space exploration techniques
F. De Bernardinis, Dept. of Electr. Eng., California Comput. Sci. Univ., Berkeley, CA, USA
A. Sangiovanni Vincentelli, Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 415-421
Xin Li, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Jian Wang, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Tun-Shih Chen, Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
Wanju Chiang, IBM Syst. & Technol. Group, Austin, TX, USA
pp. 422-429
A. Agarwal, Dept. of ECECS, Cincinnati Univ., OH, USA
R. Vemuri, Dept. of ECECS, Cincinnati Univ., OH, USA
pp. 430-436
Session 5C - Dynamic voltage scaling
R. Rao, NSF Center for Low Power Electron., Arizona State Univ., Tempe, AZ, USA
S. Vrudhula, NSF Center for Low Power Electron., Arizona State Univ., Tempe, AZ, USA
pp. 439-445
B. Mochocki, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
B. Mochocki, NSF Center for Low Power Electron., Arizona State Univ., Tempe, AZ, USA
R. Racu, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Ernst, Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
pp. 446-449
Jaewon Seo, KAIST, Daejeon, South Korea
Taewhan Kim, NSF Center for Low Power Electron., Arizona State Univ., Tempe, AZ, USA
N.D. Dutt, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 450-455
F. Li, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
G. Chen, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 456-460
Session 5D - Biochips and DNA-Based nanofabrication
T. Mukherjee, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 463-470
P.W.K. Rothemund, Comput. Sci. & Comput. & Neural Syst., California Inst. of Technol., Pasadena, CA, USA
pp. 471-478
E. Dubrova, R. Inst. of Technol., Kista, Sweden
M. Teslenko, R. Inst. of Technol., Kista, Sweden
A. Martinelli, R. Inst. of Technol., Kista, Sweden
pp. 479-484
Session 6A - Efficient simulation and synthesis methodologies for analog circuits
B. Bond, Res. Lab. in Electron., Massachusetts Inst. of Technol., Cambridge, MA, USA
L. Daniel, R. Inst. of Technol., Kista, Sweden
pp. 487-494
Bo Hu, Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
C.-J.R. Shi, R. Inst. of Technol., Kista, Sweden
pp. 495-501
A. Nieuwoudt, Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
Y. Massoud, Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
pp. 502-507
Session 6B - Technology mapping and timing analysis
A.K. Singh, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M. Mani, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M. Orshansky, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 511-518
S. Chatterjee, Dept. of Electr. Eng. & Comput. Sci.,, UC Berkeley, CA, USA
A. Mishchenko, Dept. of Electr. Eng. & Comput. Sci.,, UC Berkeley, CA, USA
R. Brayton, Dept. of Electr. Eng. & Comput. Sci.,, UC Berkeley, CA, USA
X. Wang, Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
T. Kam, IBM Syst. & Technol. Group, Austin, TX, USA
pp. 519-526
Shuo Zhou, California Univ., La Jolla, CA, USA
Bo Yao, California Univ., La Jolla, CA, USA
Hongyu Chen, California Univ., La Jolla, CA, USA
Yi Zhu, California Univ., La Jolla, CA, USA
Chung-Kuan Cheng, California Univ., La Jolla, CA, USA
pp. 527-531
Session 6C - Power aware system architecture and software optimizations
P. Suaris, Intel Corp., Hillsboro, OR, USA
Taeho Kgil, California Univ., La Jolla, CA, USA
K. Bowman, California Univ., La Jolla, CA, USA
V. De, California Univ., La Jolla, CA, USA
T. Mudge, California Univ., La Jolla, CA, USA
pp. 535-540
M. Ghoneima, Dept. of Electr. & Comput. Eng.,, Northwestern Univ., Evanston, IL, USA
Y. Ismail, Dept. of Electr. & Comput. Eng.,, Northwestern Univ., Evanston, IL, USA
M. Khellah, California Univ., La Jolla, CA, USA
J. Tschanz, California Univ., La Jolla, CA, USA
V. De, California Univ., La Jolla, CA, USA
pp. 541-546
G. Stiff, Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
F. Vahid, Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
pp. 547-554
Session 6D - Cellular array architectures
A. Chaudhary, Dept. of Comp. Sci. & Eng., Notre Dame Univ., IN, USA
D.Z. Chen, Dept. of Comp. Sci. & Eng., Notre Dame Univ., IN, USA
D.Z. Chen, Dept. of Comp. Sci. & Eng., Notre Dame Univ., IN, USA
K. Whitton, Dept. of Comp. Sci. & Eng., Notre Dame Univ., IN, USA
M. Niemier, California Univ., La Jolla, CA, USA
pp. 565-571
Session 7A - Variability aware clocking
Jeng-Liang Tsai, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Lizheng Zhang, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Lizheng Zhang, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 575-581
Minsik Cho, Dept of ECE, Texas Univ., Austin, TX, USA
S. Ahmedtt, Dept of ECE, Texas Univ., Austin, TX, USA
D.Z. Pan, Dept of ECE, Texas Univ., Austin, TX, USA
pp. 582-587
W.-C.D. Lam, Dept. of Electr. & Comput. Eng.,, Purdue Univ., W. Lafayette, IN, USA
J. Jam, Dept. of Electr. & Comput. Eng.,, Purdue Univ., W. Lafayette, IN, USA
C.-K. Koh, Dept. of Electr. & Comput. Eng.,, Purdue Univ., W. Lafayette, IN, USA
V. Balakrishnan, Dept. of Electr. & Comput. Eng.,, Purdue Univ., W. Lafayette, IN, USA
Y. Chen, California Univ., La Jolla, CA, USA
pp. 588-591
G. Venkataraman, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
N. Jayakumar, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
J. Hu, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
P. Li, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Sunil Khatri, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 592-596
Session 7B - Oscillator analysis
Ting Mei, Minnesota Univ., Twin Cities, MN, USA
J. Roychowdhury, Minnesota Univ., Twin Cities, MN, USA
pp. 604-609
K.D. Boianapally, Dept. of Electr. & Comput. Eng.,, Minnesota Univ., Minneapolis, MN, USA
Ting Mei, Dept. of Electr. & Comput. Eng.,, Minnesota Univ., Minneapolis, MN, USA
J. Roychowdhury, Dept. of Electr. & Comput. Eng.,, Minnesota Univ., Minneapolis, MN, USA
pp. 610-613
A. Mehrotra, Berkeley Design Autom., Santa Clara, CA, USA
Suihua Lu, Berkeley Design Autom., Santa Clara, CA, USA
D.C. Lee, Berkeley Design Autom., Santa Clara, CA, USA
A. Narayan, Berkeley Design Autom., Santa Clara, CA, USA
pp. 618-623
Session 7C - Power noise and thermal issues
Chao-Yang Yeh, Apache Design Solutions Inc., Mountain View, CA, USA
M. Marek-Sadowska, Berkeley Design Autom., Santa Clara, CA, USA
pp. 627-634
Yong Zhan, Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
S.S. Sapatnekar, Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
pp. 635-638
Pu Liu, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Zhenyu Qi, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Hang Li, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Lingling Jin, Berkeley Design Autom., Santa Clara, CA, USA
Wei Wu, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 639-644
Session 7D - Nanocomputing
S.C. Goldstein, Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 655-661
C. Dwyer, Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 662-667
Session 8A - Extraction and modeling for interconnect structures
Zhenhai Zhu, Cadence Berkeley Labs, CA, USA
J. White, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
pp. 675-682
Rong Jiang, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Wenyin Fu, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
J.M. Wang, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
V. Lin, Berkeley Design Autom., Santa Clara, CA, USA
C.C.-P. Chen, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 683-690
M. Mondal, Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
Y. Massoud, Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
pp. 691-696
Session 8B - Timing and power optimization
Yaping Zhan, Dept. of ECE, Carnegie Mellon Univ., Pittsburgh, PA, USA
A.J. Strojwas, Dept. of ECE, Carnegie Mellon Univ., Pittsburgh, PA, USA
M. Sharma, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
D. Newmark, Berkeley Design Autom., Santa Clara, CA, USA
pp. 699-704
S. Shah, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
A. Srivastava, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
D. Sharma, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
D. Sylvester, Berkeley Design Autom., Santa Clara, CA, USA
D. Blaauw, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 705-712
Sarvesh Bhardwaj, Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
Sarma Vrudhula, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 713-718
Session 8C - System-level variability modeling
Xin Li, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Jiayong Le, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
L.T. Pileggi, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
A. Strojwas, Berkeley Design Autom., Santa Clara, CA, USA
pp. 721-727
J.M. Wang, Arizona Univ., Tucson, AZ, USA
B. Srinivas, Arizona Univ., Tucson, AZ, USA
Dongsheng Ma, Arizona Univ., Tucson, AZ, USA
C.C.-P. Chen, Arizona Univ., Tucson, AZ, USA
Jun Li, Arizona Univ., Tucson, AZ, USA
pp. 728-735
A. Agarwal, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Kunhyuk Kang, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 736-741
Session 8D - Routing
J. Cong, Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
Yan Zhang, Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
pp. 745-752
Jia-Wei Fang, Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
I-Jye Lin, Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
Ping-Hung Yuh, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Yao-Wen Chang, Arizona Univ., Tucson, AZ, USA
Jyh-Herng Wang, Arizona Univ., Tucson, AZ, USA
pp. 753-758
M.M. Ozdal, Intel Corp., Hillsboro, OR, USA
M.D.F. Wong, Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
P.S. Honsinger, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 759-766
M.M. Ozdal, Intel Corp., Hillsboro, OR, USA
M.D.F. Wong, Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
P.S. Honsinger, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 767-774
Session 9A - New frontiers in high-level synthesis
Aravind Vijayakumar, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
F. Brewer, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 777-783
D.L. Rosenband, CSAIL, Massachusetts Inst. of Technol., USA
D.L. Rosenband, CSAIL, Massachusetts Inst. of Technol., USA
pp. 784-791
L. Singhal, Donald Bren Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
E. Bozorgzadeh, Donald Bren Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 792-797
Ngai Wong, Dept. of Electr. & Electron. Eng., Hong Kong Univ., China
V. Balakrishnan, Donald Bren Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 801-805
Xin Li, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Peng Li, Donald Bren Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
L.T. Pileggi, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 806-812
D. Vasilyev, Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
J. White, Donald Bren Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 813-820
Pu Liu, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
S.X.-D. Tan, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Hang Li, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Zhenyu Qi, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Jun Kong, Arizona Univ., Tucson, AZ, USA
pp. 821-826
Session 9C - Statistical timing analysis
K.R. Heloue, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
F.N. Najm, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 829-836
D. Sinha, Dept. of Electr. & Comput. Eng.,, Northwestern Univ., Evanston, IL, USA
Hai Zhou, Dept. of Electr. & Comput. Eng.,, Northwestern Univ., Evanston, IL, USA
pp. 837-843
Xin Li, Extreme DA, Palo Alto, CA, USA
Jiayong Le, Extreme DA, Palo Alto, CA, USA
Mustafa Celik, Extreme DA, Palo Alto, CA, USA
L.T. Pileggi, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
pp. 844-851
Session 9D - Problem structure in formal verification
P. Manolios, Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
S.K. Srinivasan, Extreme DA, Palo Alto, CA, USA
pp. 855-862
P. Manolios, Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
S.K. Srinivasan, Extreme DA, Palo Alto, CA, USA
pp. 863-870
M.F. Ali, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
S. Safarpour, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
A. Veneris, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
M.S. Abadir, Dept. of Electr. Eng., California Univ., Riverside, CA, USA
R. Drechsler, Arizona Univ., Tucson, AZ, USA
pp. 871-876
R. Armoni, Intel Corp., Moscow, Russia
S. Egorov, Intel Corp., Moscow, Russia
R. Fraer, Intel Corp., Moscow, Russia
D. Korchemny, Intel Corp., Moscow, Russia
M.Y. Vardi, Arizona Univ., Tucson, AZ, USA
pp. 877-884
Suchismita Roy, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Sayantan Das, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Prasenjit Basu, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Pallab Dasgupta, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P.P. Chakrabarti, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 885-888
Session 10A - Analytical placement
A.B. Kahng, Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
S. Reda, Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
Qinke Wang, Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
pp. 891-898
K. Vorwerk, Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
A. Kennings, Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 899-904
Haifeng Qian, Minnesota Univ., Minneapolis, MN, USA
S.S. Sapatnekar, Minnesota Univ., Minneapolis, MN, USA
pp. 905-909
Session 10B - Embedded tutorial: hardware and software design of energy efficient sensor platforms
P.H. Chou, Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
Chulsung Park, Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 913-920
B. Schott, Inf. Sci. Inst., Southern California Univ., Arlington, VA, USA
M. Bajura, Inf. Sci. Inst., Southern California Univ., Arlington, VA, USA
pp. 921-924
P.K. Dutta, Div. of Comput. Sci., California Univ., Berkeley, CA, USA
D.E. Culler, Div. of Comput. Sci., California Univ., Berkeley, CA, USA
pp. 925-932
Session 10C - Improving the accuracy of static timing analysis
A. Shebaita, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
C. Amin, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
F. Dartu, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Y. Ismail, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 935-938
H. Chen, UC San Diego, CA, USA
C. Yeh, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
G. Wilke, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
S. Reddy, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
H. Nguyen, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 939-946
A. Jain, Michigan Univ., Ann Arbor, MI, USA
D. Blaauw, Michigan Univ., Ann Arbor, MI, USA
V. Zolotov, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 947-953
M. Becer, CLK Design Autom., Littleton, MA, USA
V. Zolotov, Michigan Univ., Ann Arbor, MI, USA
R. Panda, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
A. Grinshpon, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
I. Algol, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 954-961
Session 10D - Embedded tutorial : formal eguivalence checking between system-level models and RTL
A. Koelbl, Synopsys, Inc., Mountain View, CA, USA
Yuan Lu, Michigan Univ., Ann Arbor, MI, USA
A. Mathur, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 965-971
Session 11A - Embedded tutorial: emergent communication
M.F. Chang, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 975-978
K.K. O, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
K. Kim, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
B. Floyd, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J. Mehta, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
H. Yoon, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
C.-M. Hung, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
D. Bravo, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
T. Dickson, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
X. Guo, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
R. Li, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
N. Trichy, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J. Caserta, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
W. Bomstad, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J. Branch, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
D.-J. Yang, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J. Bohorquez, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J. Chen, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
E.-Y. Seok, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
L. Gao, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
A. Sugavanam, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J.-J. Lin, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
S. Yu, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
C. Cao, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
M.-H. Hwang, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
Y.-R. Ding, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
S.-H. Hwang, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
H. Wu, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
N. Zhang, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J.E. Brewer, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
pp. 979-984
M.P. Flynn, Michigan Univ., Ann Arbor, MI, USA
J.J. Kang, Michigan Univ., Ann Arbor, MI, USA
pp. 985-992
Session 11B - Addressing emerging challenges for SoCs
T. Ishihara, Adv. CAD Technol., Fujitsu Labs. of America, Inc., Sunnyvale, CA, USA
F. Fallah, Adv. CAD Technol., Fujitsu Labs. of America, Inc., Sunnyvale, CA, USA
pp. 995-1001
F. Li, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
G. Chen, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
I. Kolcu, Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
pp. 1002-1005
A. Agiwal, Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC, USA
M. Singh, Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC, USA
pp. 1006-1013
M. Singh, Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea
M. Singh, Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea
pp. 1014-1020
Session 11C - Statistical optimization
K. Chopra, Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
S. Shah, Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
A. Srivastava, Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
D. Blaauw, Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
D. Sylvester, Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
pp. 1023-1028
M.R. Guthaus, Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
N. Venkateswarant, Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
C. Visweswariaht, Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
V. Zolotov, Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
pp. 1029-1036
D. Sinha, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
N.V. Shenoy, Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
Hai Zhou, Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
pp. 1037-1041
Session 11D - Making model checking practical
Kai-hui Chang, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, IL, USA
V. Bertacco, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, IL, USA
I.L. Markov, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, IL, USA
pp. 1045-1051
A.A. Bayazit, Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Malik, Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 1052-1059
F. Zaraket, Dept. of Electr. Eng., Princeton Univ., NJ, USA
J. Baumgartner, Dept. of Electr. Eng., Princeton Univ., NJ, USA
A. Aziz, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, IL, USA
pp. 1060-1067
M.D. Nguyen, Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
D. Stoffel, Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
M. Wedler, Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
W. Kunz, Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
pp. 1068-1075
P. Bjesse, Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
J. Kukula, Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
pp. 1076-1082
Author Index (Abstract)
pp. 1083-1088
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