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2004 International Conference on Computer Aided Design (ICCAD'04)
San Jose, CA, USA
November 07-November 11
ISBN: 0-7803-8702-3
Table of Contents
FrontMatter
Conference Committee
Foreword
ICCAD-2004 Awards
ICCAD-2004 Technical Program Committee
ICCAD-2004 Reviewers
Problems or opportunities? Beyond the 90nm frontier [Keynote]
Best practices in low power design. 1. Power reduction techniques [Tutorial 1]
Physical design at 90nm and beyond [Tutorial 2]
Signal integrity and reliability of integrated circuits: practical cons erations at 130nm and below [Tutorial 3]
Best practices in low-power design. 2. Industrial power reduction experiences [Tutorial 4]
Challenges and solutions in the design of high-frequency global clock distributions [Tutorial 5]
What's new in algorithms for cad since you left school? [Tutorial 6]
IC design in 65 nm and beyond: evolution or revolution? [Sunday Panel]
Divine for dollars [Monday Panel]
Session 1A: Statistical Modeling and Optimization Methodologies
Xin Li, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Jiayong Le, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
P. Gopalakrishnan, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 2-9
S. Mukhopadhyay, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
H. Mahmoodi, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 10-13
D. Sinha, Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Hai Zhou, Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 14-19
Session 1B: System-level Energy Management
Jinfeng Liu, Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
P.H. Chou, Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 21-28
Kihwan Choi, Dept. of Electr. Eng. Syst., Southern California Univ., Los Angeles, CA, USA
Wonbok Lee, Dept. of Electr. Eng. Syst., Southern California Univ., Los Angeles, CA, USA
R. Soma, Dept. of Electr. Eng. Syst., Southern California Univ., Los Angeles, CA, USA
M. Pedram, Dept. of Electr. Eng. Syst., Southern California Univ., Los Angeles, CA, USA
pp. 29-34
Dakai Zhu, Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
R. Melhem, Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
D. Mosse, Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
pp. 35-40
Session 1C: Eouivalence Verification
P. Bjesse, Synopsys Inc., Mountain View, CA, USA
A. Boralv, Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
pp. 42-49
Session 1D: Advances in Interconnect Analysis
Yangfeng Su, Dept. of Math., Fudan Univ., Shanghai, China
Jian Wang, Intel, Haifa, Israel
Xuan Zeng, Intel, Haifa, Israel
Zhaojun Bai, Intel, Haifa, Israel
pp. 74-79
J. Jain, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Cheng-Kok Koh, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
V. Balakrishnan, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 93-98
Session 2A: Soft Error Rate Analysis
Quming Zhou, Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
K. Mohanram, Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
pp. 100-106
S. Srinivasan, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
A. Gayasen, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
N. Vijaykrishnan, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
M. Kandemir, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
Y. Xie, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
pp. 107-110
Ming Zhang, Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
N.R. Shanbhag, Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 111-118
Session 2B: Application Specific Memory and Processor Architecture Design Techniques
M. Kandemir, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
G. Chen, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
I. Kolcu, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
pp. 120-124
K. Patel, Politecnico di Torino, Italy
E. Macii, Politecnico di Torino, Italy
L. Benini, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M. Poncino, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
pp. 125-130
M. Poncino, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Jianwen Zhu, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 131-136
Session 2C: Embedded Tutorial: The Care and Feeding of Your Statistical Static Timer
S.R. Nassif, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
D. Boning, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
N. Hakim, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 138-139
Session 3A: Crosstalk-Aware Timing and Noise Analysis
A. Kasnavi, Synopsys, Inc., Mountain View, CA, USA
J.W. Wang, Synopsys, Inc., Mountain View, CA, USA
M. Shahram, Synopsys, Inc., Mountain View, CA, USA
J. Zejda, Synopsys, Inc., Mountain View, CA, USA
pp. 141-146
I. Keller, Cadence Design Syst., San Jose, CA, USA
Ken Tseng, Cadence Design Syst., San Jose, CA, USA
N. Verghese, Cadence Design Syst., San Jose, CA, USA
pp. 147-154
Ruiming Chen, Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Hai Zhou, Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 155-159
A. Glebov, Microstyle, Moscow, Russia
S. Gavrilov, Microstyle, Moscow, Russia
R. Soloviev, Microstyle, Moscow, Russia
V. Zolotov, Synopsys, Inc., Mountain View, CA, USA
M.R. Becer, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
C. Oh, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
pp. 160-167
Session 3B: System Software Optimizations
A. Hosangadi, California Univ., Santa Barbara, CA, USA
F. Fallah, Microstyle, Moscow, Russia
R. Kastner, Microstyle, Moscow, Russia
pp. 169-174
M. Puschel, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
A.C. Zelinski, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.C. Hoe, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 175-182
N. Cheung, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
S. Parameswarani, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
J. Henkel, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 183-189
A.C. Nacul, Dept. of Comput. Sci., California Univ., Irvine, CA, USA
T. Givargis, Dept. of Comput. Sci., California Univ., Irvine, CA, USA
pp. 190-196
Session 3C: New Directions in Verification
A. Das, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P. Basu, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A. Banerjee, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P. Dasgupta, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P.P. Chakrabarti, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
C. Rama Mohan, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
pp. 198-203
M. Fahim Ali, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
A. Veneris, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
A. Smith, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
S. Safarpour, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
R. Drechsler, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
M. Abadir, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
pp. 204-209
S. Gupta, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
B.H. Krogh, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 210-217
Young-Il Kim, Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Chong-Min Kyung, Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
pp. 218-221
Session 3D: Algorithms and Modeling Techniques for Bio and Nano Technologies
Fei Su, Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
K. Chakrabarty, Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 223-228
A.J. Pfeiffer, Dept. of Chem. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
T. Mukherjee, Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
S. Hauan, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 229-236
Gang Li, Beckman Inst. for Adv. Sci. & Technol., Illinois Univ., Urbana, IL, USA
N.R. Aluru, Beckman Inst. for Adv. Sci. & Technol., Illinois Univ., Urbana, IL, USA
pp. 241-244
Session 4A: Developments in Timing Analysis and Optimization
Y.I. Ismail, Dept. of ECE, Northwestern Univ., Evanston, IL, USA
C.S. Amin, Dept. of ECE, Northwestern Univ., Evanston, IL, USA
pp. 246-253
C.S. Amin, Dept. of ECE, Northwestern Univ., Evanston, IL, USA
F. Dartu, Dept. of ECE, Northwestern Univ., Evanston, IL, USA
Y.I. Ismail, Dept. of ECE, Northwestern Univ., Evanston, IL, USA
pp. 254-260
O. Omedes, Cadence Design Syst., Inc., San Jose, CA, USA
M. Robert, Dept. of ECE, Northwestern Univ., Evanston, IL, USA
M. Ramdani, Dept. of ECE, Northwestern Univ., Evanston, IL, USA
pp. 261-266
Session 4B: Energy Efficiency and Interconnect Design
R. Rao, Dept. of ECE, Arizona Univ., Tucson, AZ, USA
S. Vrudhula, Dept. of ECE, Arizona Univ., Tucson, AZ, USA
pp. 268-274
V. Chandra, Tabula Inc., Santa Clara, CA, USA
H. Schmit, Tabula Inc., Santa Clara, CA, USA
A. Xu, Dept. of ECE, Northwestern Univ., Evanston, IL, USA
L. Pileggi, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 275-282
V. Seth, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Min Zhao, Tabula Inc., Santa Clara, CA, USA
Jiang Hu, Dept. of ECE, Northwestern Univ., Evanston, IL, USA
pp. 283-290
Session 4C: Floorplanning for Advanced Technologies
Lei Cheng, Dept. of Comput. Sic., Illinois Univ., Urbana, IL, USA
M.D.F. Wong, Tabula Inc., Santa Clara, CA, USA
pp. 292-299
Ping-Hung Yuh, Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chia-Lin Yang, Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Yao-Wen Chang, Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 300-305
J. Cong, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Jie Wei, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Yan Zhang, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 306-313
Session 4D: Robust Design Tools
Haifeng Qian, Minnesota Univ., Minneapolis, MN, USA
J.N. Kozhaya, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
S.R. Nassif, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
S.S. Sapatnekar, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 315-318
Peng Li, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
M. Asheghi, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
R. Chandra, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 319-326
Zhijian Lu, Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA
Wei Huang, Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA
J. Lach, Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA
M. Stan, Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA
K. Skadron, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 327-334
Session 5A: Embedded Tutorial: Variability Impact on Design
P. S. Zuchowski, IBM Microelectron. Div., USA
P. A. Habitz, IBM Microelectron. Div., USA
J. D. Hayes, IBM Microelectron. Div., USA
J. H. Oppold, IBM Microelectron. Div., USA
pp. 336-342
R. Heald, Sun Microsystems Inc., Sunnyvale, CA, USA
P. Wang, Sun Microsystems Inc., Sunnyvale, CA, USA
pp. 347-352
Session 5B: Architectural Issues in System Synthesis
Jingcao Hu, Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Marculescu, Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 354-361
A. Andrei, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
M. Schmitz, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
P. Eles, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
Z. Peng, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
B.M. Al Hashimi, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 362-369
Andhi Janapsatya, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
Sri Parameswaran, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
A. Ignjatovic, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 370-377
Session 5C: Integrated Placement Applications
A.P. Hurst, California Univ., Berkeley, CA, USA
P. Chong, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
A. Kuehlmann, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 379-386
D. Jariwala, Dept. of Comput. Sci., Illinois Univ., Chicago, IL, USA
J. Lillis, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 387-393
Chen Li, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Min Xie, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Cheng-Kok Koh, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
J. Cong, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
P.H. Madden, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 394-401
Haoxing Ren, Dept. of EElectr. & Comput. Eng., Texas Univ., Austin, TX, USA
D.Z. Pan, Dept. of EElectr. & Comput. Eng., Texas Univ., Austin, TX, USA
P.G. Villarubia, Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 402-409
Session 5D: Novel Directions in Logic Synthesis
J.-H.R. Jiang, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Mishchenko, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 411-418
S.K. Karandikar, Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
S.S. Sapatnekar, Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 419-422
A. Davoodi, Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
V. Khandelwal, Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
A. Srivastava, Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
pp. 423-427
S. Ahmand, Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA
R. Mahapatra, Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA
pp. 428-435
Session 6A: Embedded Tutorial: World-Level Methods in Formal Verification
R.E. Bryant, Carnegie Mellon Univ., Pittsburgh, PA, USA
S.K. Rajamani, Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA
pp. 437-438
Session 6B: Interconnect Coding and Optimization
F. Worm, Processor Archit. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
P. Ienne, Processor Archit. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
P. Thiran, Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
pp. 440-447
Kangmin Lee, Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Se-Joong Lee, Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Hoi-Jun Yoo, Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
pp. 448-451
Chuan Lin, Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Hai Zhou, Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 452-458
Session 6C: Statistical Timing Methods
J.D. Ma, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 460-467
R.A. Rutenbar, Dept. of ECE, California Univ., Santa Barbara, CA, USA
Li-C Wang, Dept. of ECE, California Univ., Santa Barbara, CA, USA
Kwang-Ting Cheng, Dept. of ECE, California Univ., Santa Barbara, CA, USA
S. Kundu, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
pp. 468-472
V. Khandelwal, Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
A. Davoodi, Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
A. Srivastava, Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
pp. 473-477
Session 6D: New Methods in Power Grid Analysis
N.E. Evmorfopoulos, Dept. of Comput. & Commun. Eng., Thessaly Univ., Volos, Greece
D.P. Karampatzakis, Dept. of Comput. & Commun. Eng., Thessaly Univ., Volos, Greece
G.I. Stamoulis, Dept. of Comput. & Commun. Eng., Thessaly Univ., Volos, Greece
pp. 479-484
Tsung-Hao Chen, Synopsis, Inc., Mountain View, CA, USA
Jeng-Liang Tsai, Dept. of Comput. & Commun. Eng., Thessaly Univ., Volos, Greece
Jeng-Liang Tsai, Dept. of Comput. & Commun. Eng., Thessaly Univ., Volos, Greece
T. Karnik, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
pp. 489-496
Session 7A: Advances in SAT-Based Verification
V. Durairaj, Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
P. Kalla, Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
pp. 498-501
Liang Zhang, Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA, USA
M.R. Prasad, Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
M.S. Hsiao, Dept. of Comput. & Commun. Eng., Thessaly Univ., Volos, Greece
pp. 502-509
M.K. Ganai, NEC Labs. America, Princeton, NJ, USA
A. Gupta, NEC Labs. America, Princeton, NJ, USA
P. Ashar, NEC Labs. America, Princeton, NJ, USA
pp. 510-517
Bing Li, Colorado Univ., Boulder, CO, USA
F. Somenzi, Colorado Univ., Boulder, CO, USA
pp. 518-525
Session 7B: Power and Layout-Driven Logic Optimization
Feng Gao, Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes, Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 527-532
V. Khandelwal, Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
A. Srivastava, Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
pp. 533-536
Cheng-Tao Hsieh, Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu, Taiwan
Jian-Cheng Lin, Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu, Taiwan
Shih-Chieh Chang, Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu, Taiwan
pp. 537-540
S. Chatterjee, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 541-548
Session 7C: Advances in Floorplanning and Placement
S.N. Adya, Synplicity, Inc., Sunnyvale, CA, USA
S. Chaturvedi, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
J.A. Roy, Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu, Taiwan
D.A. Papa, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
I.L. Markov, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 550-557
Bo Hu, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Marek-Sadowska, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 558-564
A.B. Kahng, Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
Q. Wang, Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
pp. 565-572
K. Vorwerk, Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
A. Kennings, Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
A. Vannelli, Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 573-580
Session 7D: Programmable Fabrics for Structured Design
Yajun Ran, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Marek-Sadowska, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 582-589
N. Jayakumar, Dept. of Ind. Eng., Texas A&M Univ., College Station, TX, USA
S.P. Khatri, Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 590-594
J.H. Anderson, Dept. of ECE, Toronto Univ., Ont., Canada
F.N. Najm, Dept. of ECE, Toronto Univ., Ont., Canada
pp. 602-609
Session 8A: New Issues in Clocking
Jeng-Liang Tsai, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
DongHyun Baik, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
C.C.-P. Chen, Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
K.K. Saluja, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
pp. 611-618
Ruiming Chen, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Hai Zhou, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 619-625
A. Kapoor, Dept. of ECE, Colorado Univ., Boulder, CO, USA
N. Jayakumar, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
S.P. Khatri, Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 626-631
Session 8B: Innovative Models/Methods in Analog and Digital Diagnosis
Xiaoqing Wen, Dept. of Comput. Sci. & Eng., Kyushu Inst. of Technol., Iizuka, Japan
Tokiharu Miyoshi, Dept. of Comput. Sci. & Eng., Kyushu Inst. of Technol., Iizuka, Japan
Seiji Kajihara, Dept. of Comput. Sci. & Eng., Kyushu Inst. of Technol., Iizuka, Japan
Laung-Terng Wang, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
K.K. Saluja, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
K. Kinoshita, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
pp. 633-640
Chunsheng Liu, Dept. of Comput. & Electron. Eng., Nebraska-Lincoln Univ., Omaha, NE, USA
pp. 648-651
Session 8C: Estimation and Management of Design Metrics
S. Ghiasi, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
E. Bozorgzadeh, Duke Univ., Durham, NC, USA
S. Choudhuri, Duke Univ., Durham, NC, USA
M. Sarrafzadeh, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
pp. 653-659
Bin Wu, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Jianwen Zhu, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
F.N. Najm, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 660-667
Lin Zhong, Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Ravi, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
A. Raghunathan, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
N.K. Jha, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
pp. 668-675
Session 8D: Advanced Analog/RF Macromodeling and Simulation
Peng Li, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 677-682
Xiaochun Duan, Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
K. Mayaram, Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
pp. 683-686
Xiaolue Lai, Dept. of Electr. & Comput. Eng., Minnesota Univ., Twin Cities, MN, USA
J. Roychowdhury, Dept. of Electr. & Comput. Eng., Minnesota Univ., Twin Cities, MN, USA
pp. 687-694
Session 9A: Estimation Techniques for Physical Design
C. Chu, Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 696-701
J.L. Wong, California Univ., Los Angeles, CA, USA
A. Davoodi, Dept. of Electr. & Comput. Eng., Minnesota Univ., Twin Cities, MN, USA
V. Khandelwal, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
A. Srivastava, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
M. Potkonjak, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 702-705
C.J. Alpert, IBM Corp., Austin, TX, USA
Jiang Hu, Dept. of Electr. & Comput. Eng., Minnesota Univ., Twin Cities, MN, USA
S.S. Sapatnekar, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
C.N. Sze, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
pp. 706-711
Session 9B: Timing Model Validation and Efficient On-Chip Test Compression
L. Lee, Dept. of ECE, UC-Santa Barbara, Santa Barbara, CA, USA
Li-C Wang, Dept. of ECE, UC-Santa Barbara, Santa Barbara, CA, USA
T.M. Mak, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Kwang-Ting Cheng, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
pp. 713-720
Wenjing Rao, Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
A. Orailoglu, Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
G. Su, Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
pp. 721-725
B. Arslan, Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
A. Orailoglu, Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
pp. 726-731
Session 9C: Embedded Tutorial: Emerging Technologies on the Design Manufacturing Interface
B. Koenemann, Cadence Design Syst., Inc., San Jose, CA, USA
pp. 733-738
M. Lavin, IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Fook-Luen Heng, IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
G. Northrop, IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 739-746
Session 9D: Optimization Techniques for FPGAs and Reconfigurability
M. Teslenko, R. Inst. of Technol., IMIT/KTH, Kista, Sweden
E. Dubrova, R. Inst. of Technol., IMIT/KTH, Kista, Sweden
pp. 748-751
D. Chen, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
J. Cong, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 752-759
Fei Li, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Yan Lin, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Lei He, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 760-765
Lei He, Sch. of Comput., National Univ. of Singapore, Singapore
T. Mitra, Sch. of Comput., National Univ. of Singapore, Singapore
Weng-Fai Wong, Sch. of Comput., National Univ. of Singapore, Singapore
pp. 766-773
Session 10A: Innovative Methods in High-Level Design
Weng-Fai Wong, MIT, Cambridge, MA, USA
R.S. Nikhil, Sch. of Comput., National Univ. of Singapore, Singapore
D.L. Rosenband, Sch. of Comput., National Univ. of Singapore, Singapore
N. Dave, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
pp. 775-782
Chao Huang, Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Ravi, Sch. of Comput., National Univ. of Singapore, Singapore
A. Raghunathan, Sch. of Comput., National Univ. of Singapore, Singapore
N.K. Jha, Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
pp. 783-790
A.K. Verma, Processor Archit. Lab., Swiss Fed. Inst. of Technol. Lausanne, Switzerland
P. Ienne, Processor Archit. Lab., Swiss Fed. Inst. of Technol. Lausanne, Switzerland
pp. 791-798
Session 10B: Power Analysis and Optimization
M. Ghonemia, Dept. of ECE, Northwestern Univ., Evanston, IL, USA
Y. Ismail, Dept. of ECE, Northwestern Univ., Evanston, IL, USA
pp. 800-807
A. Srivastava, Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
D. Sylvester, Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
pp. 808-813
M. Hashimoto, Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
J. Yamaguchi, Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
H. Onodera, Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
pp. 814-820
Session 10C: Routing
M.M. Ozdal, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
M.D.F. Wong, Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
pp. 822-829
M.M. Ozdal, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
M.D.F. Wong, Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
pp. 830-837
R. Fung, Toronto Technol. Center, Altera Corp., Toronto, Ont., Canada
V. Betz, Toronto Technol. Center, Altera Corp., Toronto, Ont., Canada
W. Chow, Toronto Technol. Center, Altera Corp., Toronto, Ont., Canada
pp. 838-845
Session 10D: Analog Sizing and Optimization
G. Stehr, Inst. for Electron. Design Autom., TU Munich, Germany
H. Graeb, Inst. for Electron. Design Autom., TU Munich, Germany
K. Antreich, Inst. for Electron. Design Autom., TU Munich, Germany
pp. 847-854
Xin Li, Dept. of Electr. & Comput. Eng.,, Carnegie Mellon Univ., Pittsburgh, PA, USA
P. Gopalakrishnan, Dept. of Electr. & Comput. Eng.,, Carnegie Mellon Univ., Pittsburgh, PA, USA
Yang Xu, Dept. of Electr. & Comput. Eng.,, Carnegie Mellon Univ., Pittsburgh, PA, USA
T. Pileggi, Dept. of Electr. & Comput. Eng.,, Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 855-862
Jintae Kim, Dept. of Electr. Eng., Californica Univ., Los Angeles, CA, USA
Jaeseo Lee, Dept. of Electr. Eng., Californica Univ., Los Angeles, CA, USA
L. Vandenberghe, Dept. of Electr. Eng., Californica Univ., Los Angeles, CA, USA
L. Vandenberghe, Dept. of Electr. Eng., Californica Univ., Los Angeles, CA, USA
pp. 863-870
Session 11A: Variational Analysis of Interconnects
J. Wang, Dept. of ECE, Arizona Univ., Tucson, AZ, USA
P. Ghanta, Dept. of ECE, Arizona Univ., Tucson, AZ, USA
S. Vrudhula, Dept. of ECE, Arizona Univ., Tucson, AZ, USA
pp. 880-886
Zhenhai Zhu, Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
J. White, Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
A. Demir, Dept. of ECE, Arizona Univ., Tucson, AZ, USA
pp. 887-891
Session 11B: Test Generation for New Fault Models and Circuits
D. Maruyama, Fujitsu Ltd., Kawasaki, Japan
A. Kanuma, Fujitsu Ltd., Kawasaki, Japan
T. Mochiyama, Fujitsu Ltd., Kawasaki, Japan
H. Komatsu, Fujitsu Ltd., Kawasaki, Japan
Y. Sugiyama, Fujitsu Ltd., Kawasaki, Japan
N. Ito, Fujitsu Ltd., Kawasaki, Japan
pp. 893-898
E. Chmelar, Center for Reliable Comput., Stanford Univ., Palo Alto, CA, USA
pp. 899-902
Feng Shi, Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
Y. Makris, Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
pp. 903-908
Session 11C: Embedded Tutorials: How to Bridge the Abstraction Gap in System Level Modeling and Design?
A. Bernstein, Intel Corp., Haifa, Israel
M. Burton, Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
F. Ghenassia, Fujitsu Ltd., Kawasaki, Japan
pp. 910-914
Session 11D: Hierarchical Mixed-Signal Modeling and Design
F. Ghenassia, Samsung, South Korea
N. Vijaykrishnan, Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
M.J. Irwin, Fujitsu Ltd., Kawasaki, Japan
pp. 916-922
F. De Bernarclinis, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
S. Gambini, Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
R. Vincis, Fujitsu Ltd., Kawasaki, Japan
F. Svelto, Fujitsu Ltd., Kawasaki, Japan
pp. 923-930
Author Index (PDF)
pp. 939-942
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