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Computer-Aided Design, International Conference on (2003)
San Jose, CA
Nov. 9, 2003 to Nov. 13, 2003
ISBN: 1-58113-762-1
TABLE OF CONTENTS
Foreword (PDF)
pp. iv
Awards (PDF)
pp. v
Reviewers (PDF)
pp. viii
Keynote (PDF)
pp. x
Session 1A: Interconnect-Centric SoC Design
N. Vijaykrishnan , Pennsylvania State University, University Park, PA
Mahmut Kandemir , Pennsylvania State University, University Park, PA
Lin Li , Pennsylvania State University, University Park, PA
pp. 2
Ruibing Lu , Purdue University, West Lafayette, IN
pp. 8
Chung-Kuan Cheng , University of California at San Diego, La Jolla
Andrew B. Kahng , University of California at San Diego, La Jolla
Ion Mandoiu , University of Connecticut, Storrs
Qinke Wang , University of California at San Diego, La Jolla
Hongyu Chen , University of California at San Diego, La Jolla
pp. 13
Session 1B: Energy Optimization using Dynamic Voltage Scaling for Embedded Systems
Le Yan , Princeton University, NJ
Jiong Luo , Princeton University, NJ
Niraj K. Jha , Princeton University, NJ
pp. 30
Session 1C: New Opportunities in High-Level Synthesis
Qi Wang , Cadence Design Systems, Inc, San Jose
pp. 39
Srivaths Ravi , NEC Laboratories America, Princeton, NJ
Anand Raghunathan , NEC Laboratories America, Princeton, NJ
Chao Huang , Princeton University, NJ
pp. 46
Seda Ogrenci Memik , University of California, Los Angeles
Bo-Kyung Choi , University of California, Los Angeles
Majid Sarrafzadeh , University of California, Los Angeles
pp. 54
Session 1D: New Ideas in Placement and Floorplanning
Xiaoping Tang , Cadence Design Systems, San Jose, CA
Hua Xiang , UIUC, Urbana, IL
pp. 66
Peter G. Sassone , Georgia Institute of Technology, Atlanta
pp. 74
Cristinel Ababei , University of Minnesota, Minneapolis
pp. 81
Brent Goplen , University of Minnesota, Minneapolis
Sachin Sapatnekar , University of Minnesota, Minneapolis
pp. 86
Session 2A: Improvements in SoC Testing
Ozgur Sinanoglu , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 91
Sule Ozev , Duke University, Durham, NC
Anuja Sehgal , Duke University, Durham, NC
pp. 95
Yu Xia , Portland State University, OR
Malgorzata Chrzanowska-Jeske , Portland State University, OR
Benyi Wang , Portland State University, OR
Marcin Jeske , Portland State University, OR
pp. 100
Session 2B: Electrical and Power Models - System to Transistor Level
Lukusa Kabulepa , Darmstadt University of Technology
Alberto Garcia-Ortiz , Darmstadt University of Technology
Manfred Glesner , Darmstadt University of Technology
pp. 107
Kamal Khouri , Motorola Inc., Austin, TX
Nikil Dutt , University of California, Irvine
Magdy Abadir , Motorola Inc., Austin, TX
pp. 113
S. Gavrilov , Microstyle - Moscow, Russia
A. Glebov , Microstyle - Moscow, Russia
Y. Egorov , Microstyle - Moscow, Russia
V. Zolotov , Motorola, Inc. - Austin, TX
D. Blaauw , Univ. of Michigan - Ann Arbor, MI
R. Panda , Motorola, Inc. - Austin, TX
M. Becer , Motorola, Inc. - Austin, TX
A. Ardelea , Motorola, Inc. - Austin, TX
A. Patel , Motorola, Inc. - Austin, TX
pp. 120
Session 2C: Embedded Tutorial: Design and CAD Challenges for sub-90nm CMOS Technology
Kerry Bernstein , IBM Thomas J Watson Research Center, Yorktown Hts, NY
Ching-Te Chuang , IBM Thomas J Watson Research Center, Yorktown Hts, NY
Rajiv Joshi , IBM Thomas J Watson Research Center, Yorktown Hts, NY
Ruchir Puri , IBM Thomas J Watson Research Center, Yorktown Hts, NY
pp. 129
Session 3A: Emerging Techniques in Dynamic Verification
In-Cheol Park , KAIST - Daejeon, Korea
Sehyeon Kang , KAIST - Daejeon, Korea
Yongseok Yi , KAIST - Daejeon, Korea
pp. 138
Carl Pixley , Synopsys, Hillsboro, OR
Jun Yuan , Verplex Systems, Milpitas, CA
Ken Albin , Motorola Inc., Austin, TX
pp. 142
Yunshan Zhu , Synopsys, Inc., Mountain View, CA
pp. 146
Alan J. Hu , University of British Columbia
Jeremy Casas , Intel Corporation
Jin Yang , Intel Corporation
pp. 154
Session 3B: Delay and Signal Modeling for Timing Analysis
Florentin Dartu , Intel Corporation, Hillsboro, OR
Chirayu S. Amin , Northwestern Univ., Evanston, IL
pp. 161
Yuji Yamada , Kyoto University
Hidetoshi Onodera , Kyoto University
pp. 169
Rubil Ahmadi , University of Toronto, Canada
Farid N. Najm , University of Toronto, Canada
pp. 176
David Blaauw , University of Michigan, Ann Arbor, MI
Vladimir Zolotov , Motorola, Inc., Austin, TX
Sanjay Pant , University of Michigan, Ann Arbor, MI
Rajendran Panda , Motorola, Inc., Austin, TX
pp. 184
Session 3C: Software Techniques for Energy and Performance Optimization in Embedded Systems
M. Kandemir , Pennsylvania State University, University Park, PA
A. Nadgir , Pennsylvania State University, University Park, PA
U. Sezer , University of Wisconsin, Madison, WI
pp. 193
Jinfeng Liu , University of California, Irvine
Pai H. Chou , University of California, Irvine
pp. 201
Krishnendu Chakrabarty , Duke University, Durham, NC
Ying Zhang , Duke University, Durham, NC
pp. 209
Session 3D: Optimization of Global Interconnects
Chuan Lin , Northwestern University, Evanston, IL
Hai Zhou , Northwestern University, Evanston, IL
pp. 215
Evangeline F. Y. Young , The Chinese University of Hong Kong
Dennis K. Y. Tong , The Chinese University of Hong Kong
Sampath Dechu , Micron Technology, Inc., Boise, ID
pp. 221
Stephan Held , University of Bonn, Germany
Bernhard Korte , University of Bonn, Germany
Jens Ma?berg , University of Bonn, Germany
Matthias Ringe , IBM Deutschland Entwicklung GmbH
Jens Vygen , University of Bonn, Germany
pp. 232
Session 4A: Numerical Methods for Analog Optimization and Analysis
Guido Stehr , Technical University of Munich, Germany
Frank Schenkel , MunEDA GmbH, Germany
Helmut Graeb , Technical University of Munich, Germany
Kurt Antreich , Technical University of Munich, Germany
pp. 241
Piet Vanassche , Katholieke Universiteit Leuven - ESAT/MICAS, Belgium
Willy Sansen , Katholieke Universiteit Leuven - ESAT/MICAS, Belgium
pp. 247
Session 4B: CAD Algorithms for Emerging Technologies
Gerhard W. Dueck , University of New Brunswick, Fredericton
Dmitri Maslov , University of New Brunswick, Fredericton
pp. 256
Ion Mandoiu , University of Connecticut
Andrew B. Kahng , University of California at San Diego
Xu Xu , University of California at San Diego
Alex Z. Zelikovsky , Georgia State University
pp. 262
S. K. De , University of Illinois at Urbana-Champaign
N. R. Aluru , University of Illinois at Urbana-Champaign
pp. 270
Session 4C: Design Techniques for Customized Processors
Claire F. Fang , Carnegie Mellon University, Pittsburgh, PA
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, PA
Tsuhan Chen , Carnegie Mellon University, Pittsburgh, PA
pp. 275
Srivaths Ravi , NEC Laboratories America, Princeton, NJ
Anand Raghunathan , NEC Laboratories America, Princeton, NJ
Niraj K. Jha , Princeton University, Princeton, NJ
pp. 283
Newton Cheung , University of New South Wales, Australia
Sri Parameswaran , University of New South Wales, Australia
J? Henkel , NEC Laboratories America, Princeton, NJ
pp. 291
Session 4D: New Improvements in Placement
Tony F. Chan , UCLA Mathematics Department
Tim Kong , Magma Design Automation
Joseph R. Shinnerl , UCLA Computer Science Department
Kenton Sze , UCLA Mathematics Department
pp. 299
Mehmet Can YILDIZ , SUNY Binghamton Computer Science Department
Ateen Khatkhate , SUNY Binghamton Computer Science Department
Ajita Mathur , SUNY Binghamton Computer Science Department
Satoshi Ono , SUNY Binghamton Computer Science Department
Patrick H. Madden , SUNY Binghamton Computer Science Department
pp. 307
Igor L. Markov , University of Michigan, Ann Arbor
Paul G. Villarrubia , IBM, Corporation, Austin, TX
pp. 311
Session 5A: Optimizations for Verification Engines
M. K. Iyer , University of California - Santa Barbara
K.-T. Cheng , University of California - Santa Barbara
pp. 320
Andreas Kuehlmann , University of California at Berkeley; Cadence Berkeley Labs, CA
Cong Liu , University of California at Berkeley
pp. 326
Chao Wang , University of Colorado at Boulder
Fabio Somenzi , University of Colorado at Boulder
pp. 334
Session 5B: System Design Concepts
Arijit Ghosh , University of California, Irvine
pp. 342
Nicholas H. Zamora , Carnegie Mellon University, Pittsburgh, PA
Phillip Stanley-Marbell , Carnegie Mellon University, Pittsburgh, PA
Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
pp. 348
Rami Beidas , University of Toronto, Canada
pp. 356
Session 5C: Analog Design and Methodology
Won Namgoong , University of Southern California
pp. 363
Mohammad Taherzadeh-Sani , University of Tehran, Iran
Reza Lotfi , University of Tehran, Iran
Omid Shoaei , University of Tehran, Iran
pp. 367
Mohammad Taherzadeh-Sani , Univ. of Tehran, Iran
M. Yaser Azizi , Univ. of Tehran, Iran
Omid Shoaei , Univ. of Tehran, Iran
pp. 371
Stefanos Sidiropoulos , Stanford University, CA; Aeluros Inc., Mt. View, CA
Mark Horowitz , Stanford University, CA
pp. 375
Session 5D: Routing
Yao-Wen Chang , National Taiwan University, Taipei
Tsung-Yi Ho , National Taiwan University, Taipei, Taiwan
D. T. Lee , Academia Sinica, Taipei, Taiwan
pp. 382
Yongseok Cheon , The University of Texas at Austin
Seokjin Lee , The University of Texas at Austin
pp. 388
Muhammet Mustafa Ozdal , Univ. of Illinois at Urbana-Champaign
Martin D. F. Wong , Univ. of Illinois at Urbana-Champaign
pp. 394
Bing Lu , Cadence Design Sys. Inc., New Providence, NJ
Anand Rajaram , Texas A&M University
Rabi Mahapatra , Texas A&M University
Jiang Hu , Texas A&M University
pp. 401
Session 6A: Automatic Abstraction for Formal Verification
Bing Li , University of Colorado at Boulder
HoonSang Jin , University of Colorado at Boulder
Gary D. Hachtel , University of Colorado at Boulder
Fabio Somenzi , University of Colorado at Boulder
pp. 408
Aarti Gupta , NEC Laboratories America, Princeton, NJ
Malay Ganai , NEC Laboratories America, Princeton, NJ
Zijiang Yang , NEC Laboratories America, Princeton, NJ
Pranav Ashar , NEC Laboratories America, Princeton, NJ
pp. 416
Curtis A. Nelson , University of Utah, Salt Lake City
Chris J. Myers , University of Utah, Salt Lake City
Tomohiro Yoneda , National Institute of Informatics, Tokyo, Japan
pp. 424
Session 6B: Embedded Tutorial: System Level Design and Verification using a Synchronous Lan
G?rard Berry , Esterel Technologies, France
Satnam Singh , Xilinx, San Jose, CA
pp. 433
Session 6C: Nonlinear Modelling of Analog and Optical Systems
Alper Demir , Ko? University, Istanbul, Turkey
pp. 441
Joel Phillips , Cadence Design Systems, San Jose, CA
Jo? Afonso , Technical University of Lisbon, Portugal
Arlindo Oliveira , Technical University of Lisbon, Portugal
L. Miguel Silveira , Technical University of Lisbon, Portugal
pp. 446
Peng Li , Carnegie Mellon University, Pittsburgh, PA
Yang Xu , Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
pp. 454
Session 6D: Timing and Tradeoffs in Placement
Wonjoon Choi , University of Minnesota, Minneapolis
Kia Bazargan , University of Minnesota, Minneapolis
pp. 463
Maogang Wang , Cadence Design Systems, San Jose, CA
Bo-Kyung Choi , University of California, Los Angeles
Majid Sarrafzadeh , University of California, Los Angeles
pp. 467
Jason Cong , University of California, Los Angeles
Michail Romesis , University of California, Los Angeles
Min Xie , University of California, Los Angeles
pp. 472
Session 7A: Simulation at the Nanometer Scale
R. Iris Bahar , Brown University, RI
Joseph Mundy , Brown University, RI
Jie Chen , Brown University, RI
pp. 480
Kaustav Banerjee , University of California Santa Barbara, CA
Florent Pegeon , Silvaco Data Systems, France
Santanu Mahapatra , Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland
pp. 497
Session 7B: Energy Issues in Systems Design
Ali Iranli , University of Southern California
Hanif Fatemi , University of Southern California
Massoud Pedram , University of Southern California
pp. 504
Praveen Kalla , Univ. of Notre Dame
Xiaobo Sharon Hu , Univ. of Notre Dame
J? Henkel , NEC Laboratories America Inc.
pp. 518
Peter Petrov , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 523
Session 7C: Constraint Driven High-Level Synthesis
Yiping Fan , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
Zhiru Zhang , University of California, Los Angeles
pp. 529
Yiping Fan , University of California, Los Angeles
Guoling Han , University of California, Los Angeles
Xun Yang , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 536
D. Helms , OFFIS Research Institute, Germany
M. Schulte , OFFIS Research Institute, Germany
A. Schulz , Univ. of Oldenburg, Germany
W. Nebel , Univ. of Oldenburg, Germany
pp. 544
Lin Zhong , Princeton University, NJ
Pallav Gupta , Princeton University, NJ
pp. 551
Session 7D: Optimal Interconnect Synthesis and Analysis
Azadeh Davoodi , University of Maryland at College Park
Akash Nanavati , University of California at Los Angeles
Ankur Srivastava , University of Maryland at College Park
pp. 560
Giuseppe S. Garcea , Delft University of Technology, The Netherlands
Nick P. van der Meijs , Delft University of Technology, The Netherlands
Ralph H. J. M. Otten , Eindhoven University of Technology, The Netherlands
pp. 568
Dian Zhou , The University of Texas at Dallas
Ruiming Li , The University of Texas at Dallas
Xuan Zeng , Fudan University, China
pp. 581
Session 8A: Memory Testing
N. Achouri , iRoC Technologies, France
S. Boutobza , iRoC Technologies, France
pp. 588
Chih-Wea Wang , National Tsing Hua University, Hsinchu, Taiwan
Jih-Nung Lee , National Tsing Hua University, Hsinchu, Taiwan
Yung-Fa Chou , National Tsing Hua University, Hsinchu, Taiwan
Chih-Tsun Huang , National Tsing Hua University, Hsinchu, Taiwan
Kuo-Liang Cheng , National Tsing Hua University, Hsinchu, Taiwan
pp. 595
Bai Hong Fang , McMaster University, Hamilton, Canada
Nicola Nicolici , McMaster University, Hamilton, Canada
pp. 599
Session 8B: Statistical Static Timing - I
Anirudh Devgan , IBM Research, Austin, TX
Chandramouli Kashyap , IBM Microelectronics, Austin, TX
pp. 607
Sarma B. K. Vrudhula , University of Arizona
Sarvesh Bhardwaj , University of Arizona
pp. 615
Session 8C: Power-Aware Design
David Blaauw , University of Michigan, Ann Arbor
Nam Sung Kim , University of Michigan, Ann Arbor
pp. 627
Krishna Sekar , UC San Diego, La Jolla
Sujit Dey , UC San Diego, La Jolla
pp. 641
Session 8D: Interconnect Reduction
Sheldon X.-D. Tan , University of California, Riverside
pp. 650
Bernard N. Sheehan , Mentor Graphics Corporation, Wilsonville, Oregon
pp. 658
D. Krishna , Rensselaer Polytechnic Institute, Troy, NY
Y. L. Le Coz , Rensselaer Polytechnic Institute, Troy, NY
W. M. Loh , LSI Logic Corporation, Milpitas, CA
P. Bendix , LSI Logic Corporation, Milpitas, CA
pp. 665
Session 9A: Embedded Tutorial: Mixed Signal DFT: A Concise Overview
Bozena Kaminska , Comet Microsystems
pp. 672
Session 9B: Embedded Tutorial: Manufacturing-Aware Physical Design
Puneet Gupta , UC San Diego, La Jolla
Andrew B. Kahng , UC San Diego, La Jolla
pp. 681
Session 9C: Cool Topics in Logic Synthesis
Frank Liu , IBM, Austin, TX
Jeffrey L. Burns , IBM, Austin, TX
Richard B. Brown , University of Michigan, Ann Arbor
pp. 689
Abdulkadir Utku Diril , Georgia Institute of Technology, Atlanta, GA
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta, GA
Yuvraj Singh Dhillon , Georgia Institute of Technology, Atlanta, GA
pp. 693
Julien Lamoureux , University of British Columbia
pp. 701
Alan Mishchenko , University of California at Berkeley
Robert K. Brayton , University of California at Berkeley
pp. 709
Session 9D: Graph Algorithmic Approaches to EDA Problems
Yongseok Cheon , The University of Texas at Austin
Martin D. F. Wong , University of Illinois at Urbana-Champaign
pp. 718
Navaratnasothie Selvakkumaran , University of Minnesota, Minneapolis
George Karypis , University of Minnesota, Minneapolis
pp. 726
Jianhua Liu , University of California, San Diego
Haikun Zhu , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
pp. 734
Lei Yang , University of Washington, Seattle
pp. 741
Session 10A: Parametric Considerations in Test Schemes
Jitin Tharian , University of Maryland, Baltimore
Jim Plusquellic , University of Maryland, Baltimore
pp. 748
Andrew B. Kahng , University of California at San Diego
Ion Mandoiu , University of Connecticut, Storrs
Puneet Gupta , University of California at San Diego
pp. 754
Aman A. Kokrady , Texas Instruments India, Bangalore, India
C. P. Ravikumar , Texas Instruments India, Bangalore, India
pp. 760
Rahul Kundu , Carnegie Mellon University, Pittsburgh, PA
R. D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh, PA
pp. 765
Session 10B: Power-Grid and Substrate Analysis
Imad A. Ferzli , University of Toronto, Canada
Farid N. Najm , University of Toronto, Canada
pp. 770
Haibo Zeng , University of California, Berkeley
Joshua L. Garrett , University of California, Berkeley
Luca Daniel , University of California, Berkeley
Alessandra Nardi , University of California, Berkeley
pp. 778
Clement Luk , University of Wisconsin-Madison
Tsung-Hao Chen , University of Wisconsin-Madison
pp. 786
Zhao Li , University of Washington, Seattle
C.-J. Richard Shi , University of Washington, Seattle
pp. 793
Session 10C: Hot Topics in Logic Synthesis
Andreas Kuehlmann , University of California at Berkeley; Cadence Berkeley Labs, Berkeley, CA
Ellen Sentovich , Cadence Berkeley Labs, Berkeley, CA
pp. 801
Shih-Hsu Huang , Chung Yuan Christian University, Chung Li, Taiwan
Yow-Tyng Nieh , Chung Yuan Christian University, Chung Li, Taiwan
pp. 809
Chao-Yang Yeh , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 813
Josep Carmona , Universitat Polit?cnica de Catalunya, Spain
Jordi Cortadella , Universitat Polit?cnica de Catalunya, Spain
pp. 818
Session 10D: Interconnect Modeling
Anne Woo , University of Illinois, Urbana
Traianos Yioultsis , Aristotle University of Thessaloniki, Greece
pp. 827
Dinesh Pamunuwa , Royal Institute of Technology, Sweden
Shauki Elassaad , Cadence Design Systems, Berkeley, CA
Hannu Tenhunen , Royal Institute of Technology, Sweden
pp. 835
Ben Song , Massachusetts Institute of Technology, Cambridge
Zhenhai Zhu , Massachusetts Institute of Technology, Cambridge
John D. Rockway , Lawrence Livemore National Laboratory, Berkeley, CA
Jacob White , Massachusetts Institute of Technology, Cambridge
pp. 843
Yu Cao , UC Berkeley
Xuejue Huang , Rambus Inc.
Dennis Sylvester , Univ. of Michigan, Ann Arbor
pp. 848
Session 11A: Test Data Reduction Techniques
Sudhakar M. Reddy , University of Iowa, Iowa City
Irith Pomeranz , Purdue University, West Lafayette, IN
Chen Wang , Mentor Graphic Corporation, Wilsonville, OR
Jerzy Tyszer , Poznan University of Technology, Poland
pp. 855
C. V. Krishna , University of Texas, Austin
pp. 863
Session 11B: Embedded Tutorial: Formal Methods for Dynamic Power Management
Rajesh K. Gupta , UC San Diego, La Jolla
Sandeep K. Shukla , Virginia Tech, Blacksburg, VA
pp. 874
Session 11C: Embedded Tutorial: Large-Scale Circuit Placement: Gap and Promise
Jason Cong , UCLA Computer Science Department
Tim Kong , Magma Design Automation
Joseph R. Shinnerl , UCLA Computer Science Department
Min Xie , UCLA Computer Science Department
Xin Yuan , UCLA Computer Science Department
pp. 883
Abhishek Ranjan , Hier Design Inc
Maogang Wang , Cadence Design Systems
pp. 891
Session 11D: Statistical Static Timing - II
Aseem Agarwal , University of Michigan, Ann Arbor
David Blaauw , University of Michigan, Ann Arbor
Vladimir Zolotov , Motorola, Inc., Austin, TX
pp. 900
Aseem Agarwal , University of Michigan, Ann Arbor
David Blaauw , University of Michigan, Ann Arbor
Vladimir Zolotov , Motorola, Inc., Austin, TX
pp. 914
Author Index (PDF)
pp. 922
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