San Jose, CA
Nov. 9, 2003 to Nov. 13, 2003
Girish Varatkar , Carnegie Mellon University, Pittsburgh, PA
In this paper, we present an interprocessor communication-aware task scheduling algorithm applicable to a multiprocessor system executing an application with dependent tasks. Our algorithm takes the application task graph and the architecture graph as inputs, assigns the tasks to processors and then schedules them. As main theoretical contribution, the algorithm we propose reduces the overall systems energy by (i) reducing the total interprocessor communication and (ii) executing certain cycles at a lower voltage level. Experimental results show that by tuning the parameter for communication awareness, a schedule using our algorithm can reduce upto 80% interprocessor communication in a complex video/audio application (compared to a schedule which is only voltage-selection aware) without losing much in the number of cycles executed at lower voltage.
low-power scheduling, dynamic voltage scaling
Girish Varatkar, "Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization", ICCAD, 2003, Computer-Aided Design, International Conference on, Computer-Aided Design, International Conference on 2003, pp. 510, doi:10.1109/ICCAD.2003.1257859