loading...
  • I
  • ICCAD
  • 2001
  • 2001 International Conference on Computer-Aided Design (ICCAD '01)
Advanced Search 
2001 International Conference on Computer-Aided Design (ICCAD '01)
San Jose, California
November 04-November 08
ISBN: 0-7803-7247-6
Table of Contents
null
Keynote (PDF)
pp. xxii
Session 1A: Dynamic Verification
Murali Kudlugi, IKOS Systems Inc., Waltham, MA
Charles Selvidge, IKOS Systems Inc., Waltham, MA
Russell Tessier, University of Massachusetts, Amherst
pp. 2
Scott Taylor, Compaq Computer Corporation
Carl Ramey, Compaq Computer Corporation
Craig Barner, Compaq Computer Corporation
David Asher, Compaq Computer Corporation
pp. 10
Session 1B: System-Level Exploration and Design
Tony Givargis, University of California, Irvine
Frank Vahid, University of California, Riverside
J?rg Henkel, C&C Research Laboratories, NEC USA, Princeton, NJ
pp. 25
Paul Lieverse, Delft University of Technology, The Netherlands
Todor Stefanov, Leiden Institute of Advanced, The Netherlands
Pieter van der Wolf, Philips Research Laboratories, The Netherlands
Ed Deprette, Leiden Institute of Advanced, The Netherlands
pp. 31
Gokhan Memik, University of California, Los Angeles
William H. Mangione-Smith, University of California, Los Angeles
Wendong Hu, University of California, Los Angeles
pp. 39
Session 1C: Interconnect Planning
Amir H. Ajami, Univ. of Southern California, Los Angeles
Kaustav Banerjee, Stanford University, CA
Massoud Pedram, Univ. of Southern California, Los Angeles
pp. 44
Xiaoping Tang, University of Texas at Austin, TX
Ruiqi Tian, University of Texas at Austin, TX
Hua Xiang, University of Texas at Austin, TX
D. F. Wong, University of Texas at Austin, TX
pp. 49
Bret Victor, University of California, Berkeley
Kurt Keutzer, University of California, Berkeley
pp. 57
Session 1D: Analog Macromodeling
Xin Li, Fudan University, Shanghai, China
Xuan Zeng, Fudan University, Shanghai, China
Dian Zhou, University of Texas at Dallas, Richardson, TX
Xieting Ling, Fudan University, Shanghai, China
pp. 65
Walter Daems, Katholieke Universiteit Leuven (Belgium)
Georges Gielen, Katholieke Universiteit Leuven (Belgium)
Willy Sansen, Katholieke Universiteit Leuven (Belgium)
pp. 70
Session 3A: Sequential Synthesis
Sequential SPFDs (Abstract)
Subarnarekha Sinha, University of California at Berkeley
Andreas Kuehlmann, Cadence Berkeley Labs, Berkeley, CA
Robert K. Brayton, University of California at Berkeley
pp. 84
Ingmar Neumann, University of Frankfurt/Main, Germany
Wolfgang Kunz, University of Frankfurt/Main, Germany
pp. 95
Nina Yevtushenko, Tomsk State University, Russia
Tiziano Villa, Via di S.Pantaleo, Italy
Robert K. Brayton, Univ. of California, Berkeley
Alex Petrenko, CRIM, Montreal, CAN
Alberto L. Sangiovanni-Vincentelli, Univ. of California, Berkeley
pp. 103
Session 3B: Compiler Techniques in System Level Design
Prabhat Jain, Massachusetts Institute of Technology, Cambridge
Srinivas Devadas, Massachusetts Institute of Technology, Cambridge
Daniel Engels, Massachusetts Institute of Technology, Cambridge
Larry Rudolph, Massachusetts Institute of Technology, Cambridge
pp. 119
Ryan Kastner, University of California, Los Angeles
Seda Ogrenci-Memik, University of California, Los Angeles
Elaheh Bozorgzadeh, University of California, Los Angeles
Majid Sarrafzadeh, University of California, Los Angeles
pp. 127
Session 3C: Routing Architecture and Techniques for FPGAs
Amit Singh, University of California, Santa Barbara
Ganapathy Parthasarathy, University of California, Santa Barbara
Malgorzata Marek-Sadowska, University of California, Santa Barbara
pp. 132
Nak-Woong Eum, Electronics & Telecom. Research Institute, Taejon Korea
Taewhan Kim, KAIST, Taejon, Korea
Chong-Min Kyung, KAIST, Taejon, Korea
pp. 137
Session 3D: Interconnect Performance and Reliability Optimization
Xiaohai Wu, Tsinghua University, Beijing, China
Xianlong Hong, Tsinghua University, Beijing, China
Yici Cai, Tsinghua University, Beijing, China
C. K. Cheng, Univ. of California at San Diego
Jun Gu, Hong Kong Univ. of Science and Technology, Hong Kong
Wayne Dai, Univ. of California at Santa Cruz
pp. 153
Kaustav Banerjee, Stanford University, CA
Amit Mehrotra, University of Illinois at Urbana-Champaign
pp. 158
Session 4A: Circuit Structure in Formal Verification
Jason Baumgartner, IBM Enterprise Systems Group, Austin, TX
Andreas Kuehlmann, Cadence Berkeley Labs, Berkeley, CA
pp. 176
Dominik Stoffel, University of Frankfurt/Main, Germany
Wolfgang Kunz, University of Frankfurt/Main, Germany
pp. 183
Ying-Tsai Chang, University of California, Santa Barbara
Kwang-Ting (Tim) Cheng, University of California, Santa Barbara
pp. 190
Session 4B: System Level Power and Performance Modeling
G. Beltrame, CEFRIEL, Milano, Italy
C. Brandolese, Politecnico di Milano, Italy
W. Fornaciari, Politecnico di Milano, Italy
F. Salice, Politecnico di Milano, Italy
D. Sciuto, Politecnico di Milano, Italy
V. Trianni, Politecnico di Milano, Italy
pp. 195
Mahmut Kandemir, Pennsylvania State University, PA
Ugur Sezer, University of Wisconsin, Madison
Victor Delaluz, Pennsylvania State University, PA
pp. 201
Radu Marculescu, Carnegie Mellon University, Pittsburgh, PA
Amit Nandi, Carnegie Mellon University, Pittsburgh, PA
Luciano Lavagno, Universita di' Udine, Italy
Alberto Sangiovanni-Vincentelli, University of California, Berkeley
pp. 207
Session 4C: Topics in Physical Synthesis
Thomas Kutzschebauch, IBM TJ Watson Research Center, Yorktown Heights, NY
Leon Stok, IBM TJ Watson Research Center, Yorktown Heights, NY
pp. 216
Hua Xiang, University of Texas at Austin, TX
Xiaoping Tang, University of Texas at Austin, TX
D. F. Wong, University of Texas at Austin, TX
pp. 232
Session 4D: Model Order Reduction
Carlos P. Coelho, IST/Technical University of Lisbon, Lisboa, Portugal
Joel R. Phillips, Cadence Design Systems, San Jose, CA
L. Miguel Silveira, IST/Technical University of Lisbon, Lisboa, Portugal
pp. 245
Session 5A: Embedded Tutorial: Embedded Software and Systems
Lothar Thiele, Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
pp. 264
D. Verkest, IMEC, Leuven, Belgium
P. Yang, IMEC, Leuven, Belgium
C. Wong, IMEC, Leuven, Belgium
P. Marchal, IMEC, Leuven, Belgium
pp. 265
Session 5B: Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design
Domine Leenaerts, Philips Research, The Netherlands
Georges Gielen, Katholieke Universiteit Leuven, Belgium
Rob A. Rutenbar, Carnegie Mellon University, U.S.A
pp. 270
Session 6A: BDDs and SAT
Pankaj Chauhan, Carnegie Mellon University, Pittsburgh, PA
Edmund M. Clarke, Carnegie Mellon University, Pittsburgh, PA
Somesh Jha, University of Wisconsin, Madison, WI
Jim Kukula, Synopsys Inc., Beverton, OR
Tom Shiple, Synopsys Inc., Beverton, OR
Helmut Veith, TU Vienna, Austria
Dong Wang, Carnegie Mellon University, Pittsburgh, PA
pp. 293
Session 6B: Convergence of Abstractions in High-Level Synthesis
Diana Marculescu, Carnegie Mellon University, Pittsburgh, PA
Anoop Iyer, Carnegie Mellon University, Pittsburgh, PA
pp. 306
Malay Haldar, Mach Design Systems, Inc.
Anshuman Nayak, Mach Design Systems, Inc.
Alok Choudhary, Northwestern University
Prith Banerjee, Northwestern University
pp. 314
Daehong Kim, Seoul National University, Korea
Jinyong Jung, Seoul National University, Korea
Sunghyun Lee, Seoul National University, Korea
Jinhwan Jeon, GCT Research, Inc., Seoul, Korea
Kiyoung Choi, Seoul National University, Korea
pp. 320
Session 6C: Signal Integrity and Clock Design
Haihua Su, University of Minnesota, Minneapolis
Sachin S. Sapatnekar, University of Minnesota, Minneapolis
pp. 333
Session 6D: Analog Synthesis
H. Graeb, Technical University of Munich
S. Zizala, Infineon Technologies, Munich
J. Eckmueller, Infineon Technologies, Munich
K. Antreich, Technical University of Munich
pp. 343
Michael J. Krasnicki, Texas Instruments Incorporated, Dallas, TX
Rodney Phelps, Carnegie Mellon University, Pittsburgh, PA
James R. Hellums, Texas Instruments Incorporated, Dallas, TX
Mark McClung, Texas Instruments Incorporated, Dallas, TX
Rob A. Rutenbar, Carnegie Mellon University, Pittsburgh, PA
L. Richard Carley, Carnegie Mellon University, Pittsburgh, PA
pp. 350
P. Vancorenland, Katholieke Universiteit Leuven, Belgium
G. Van der Plas, Katholieke Universiteit Leuven, Belgium
M. Steyaert, Katholieke Universiteit Leuven, Belgium
G. Gielen, Katholieke Universiteit Leuven, Belgium
W. Sansen, Katholieke Universiteit Leuven, Belgium
pp. 358
Session 7A: Manufacturing Test: Stuck-at to Crosstalk
Xiaoyun Sun, University of Minnesota, Minneapolis
Seonki Kim, University of Minnesota, Minneapolis
Bapiraju Vinnakota, University of Minnesota, Minneapolis
pp. 375
Session 7B: Architecture Oriented Scheduling
Carlos Alba-Pinto, Eindhoven University of Technology
Bart Mesman, Philips Research Laboratories and Eindhoven Embedded Systems Institute
Jochen Jess, Eindhoven University of Technology
pp. 384
S. Ogrenci Memik, University of California, Los Angeles
E. Bozorgzadeh, University of California, Los Angeles
R. Kastner, University of California, Los Angeles
M. Sarrafzadeh, University of California, Los Angeles
pp. 391
Session 7C: New Techniques in Routing
Fan Mo, University of California at Berkeley
Abdallah Tabbara, University of California at Berkeley
Robert K. Brayton, University of California at Berkeley
pp. 404
Charles Alpert, IBM Corporation, Austin, TX
Andrew B. Kahng, UCSD, La Jolla, CA
Bao Liu, UCSD, La Jolla, CA
Ion Mandoiu, UCSD, La Jolla, CA
Alexander Zelikovsky, Georgia State University, Atlanta, GA
pp. 408
Session 7D: Issues in Substrate Coupling
Minqing Liu, University of California, Santa Cruz
Tiejun Yu, Cadence Design Systems
Wayne W.-M. Dai, University of California, Santa Cruz
pp. 424
Session 8A: Combinational Optimization
Jan Hlavicka, Czech Technical University
Petr Fiser, Czech Technical University
pp. 439
Jennifer L. Wong, University of California, Los Angeles
Farinaz Koushanfar, University of California, Berkeley
Seapahn Meguerdichian, University of California, Los Angeles
Miodrag Potkonjak, University of California, Los Angeles
pp. 453
Session 8B: Real Time Scheduling and Performance Analysis
Amit Sinha, Massachusetts Institute of Technology, Cambridge
Anantha P. Chandrakasan, Massachusetts Institute of Technology, Cambridge
pp. 458
Session 8C: Power Analysis
Joseph N. Kozhaya, University of Illinois, Urbana
Sani R. Nassif, IBM Austin Research Labs
Farid N. Najm, University of Toronto
pp. 480
J. L. Rossello, Balearic Islands University, Palma de Mallorca, Spain
Jaume Segura, Balearic Islands University, Palma de Mallorca, Spain
pp. 494
Session 8D: Timing and Noise Analysis
Jin-Fuw Lee, IBM T. J. Watson Research Center, Yorktown Heights, NY
D. L. Ostapko, IBM T. J. Watson Research Center, Yorktown Heights, NY
Jeffery Soreff, IBM Fishkill, Hopewell Junction, NY
C. K. Wong, The Chinese Univ. of Hong Kong, Shatin
pp. 507
Alexey Glebov, MicroStyle - Moscow, Russia
Sergey Gavrilov, MicroStyle - Moscow, Russia
David Blaauw, University of Michigan
Supamas Sirichotiyakul, Motorola Inc. Austin, TX
Chanhee Oh, Motorola Inc. Austin, TX
Vladimir Zolotov, Motorola Inc. Austin, TX
pp. 515
Session 9A: System Level Test and Reliability
Erik Larsson, Link?pings Universitet, Sweden
Zebo Peng, Link?pings Universitet, Sweden
Gunnar Carlsson, Ericsson
pp. 523
Don Shaw, Gennum Corporation, Burlington, Ontario
Dhamin Al-Khalili, Royal Military College of Canada, Kingston, Ontario
C?me Rozon, Royal Military College of Canada, Kingston, Ontario
pp. 531
Session 9B: Power Issues in High Level Synthesis
Vijay Raghunathan, University of California, Los Angeles
Srivaths Ravi, NEC USA, Princeton, NJ
Anand Raghunathan, NEC USA, Princeton, NJ
Ganesh Lakshminarayana, NEC USA, Princeton, NJ
pp. 545
Chun-Gi Lyuh, Korea Advanced Institute of Science & Technology, Taejon
Taewhan Kim, Korea Advanced Institute of Science & Technology, Taejon
C. L. Liu, National Tsing Hua Univ., Hsinchu, Taiwan
pp. 553
Session 9C: Advances in Placement
Oluf Faroe, University of Copenhagen, Denmark
David Pisinger, University of Copenhagen, Denmark
Martin Zachariasen, University of Copenhagen, Denmark
pp. 565
Xiaojian Yang, University of California, Los Angeles
Ryan Kastner, University of California, Los Angeles
Majid Sarrafzadeh, University of California, Los Angeles
pp. 573
Prakash Gopalakrishnan, Carnegie Mellon University, Pittsburgh, Pennsylvania
Rob A. Rutenbar, Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 577
Session 9D: Interconnect Analysis and Extraction
Zhenhai Zhu, Massachusetts Institute of Technology, Cambridge
Jingfang Huang, University of North Carolina, Chapel Hill
Ben Song, Massachusetts Institute of Technology, Cambridge
Jacob White, Massachusetts Institute of Technology, Cambridge
pp. 592
Session 10A: Don't Care Optimization and Boolean Matching
Chih-Wei (Jim) Chang, University of California, Santa Barbara
Malgorzata Marek-Sadowska, University of California, Santa Barbara
pp. 606
Session 10B: Power Saving Techniques for Embedded Processors
Andreas Hoffmann, Integrated Signal Processing Systems, RWTH Aachen, Germany
Oliver Schliebusch, Integrated Signal Processing Systems, RWTH Aachen, Germany
Achim Nohl, Integrated Signal Processing Systems, RWTH Aachen, Germany
Gunnar Braun, Integrated Signal Processing Systems, RWTH Aachen, Germany
Oliver Wahlen, Integrated Signal Processing Systems, RWTH Aachen, Germany
Heinrich Meyr, Integrated Signal Processing Systems, RWTH Aachen, Germany
pp. 625
Subash G Chandar, Texas Instruments India Ltd., Bangalore, India
Mahesh Mehendale, Texas Instruments India Ltd., Bangalore, India
R. Govindarajan, Indian Institute of Science, Bangalore, India
pp. 631
Session 10C: Embedded Tutorial: IC Power Distribution Challenges
Sudhakar Bobba, Sun Microsystems, Inc.
Tyler Thorp, Sun Microsystems, Inc.
Kathirgamar Aingaran, Afara Websystems
Dean Liu, Sun Microsystems, Inc.
pp. 643
Shen Lin, Apache Design Solutions, Inc., Palo Alto, CA
Norman Chang, Apache Design Solutions, Inc., Palo Alto, CA
pp. 651
Session 11A: Panel: Automatic Hierarchical Design: Fantasy or Reality?
Usage of this product signifies your acceptance of the Terms of Use.