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Computer-Aided Design, International Conference on (2001)
San Jose, California
Nov. 4, 2001 to Nov. 8, 2001
ISBN: 0-7803-7247-6
TABLE OF CONTENTS
Foreword (PDF)
pp. iii
Reviewers (PDF)
pp. xiv
Keynote (PDF)
pp. xxii
Session 1A: Dynamic Verification
Charles Selvidge , IKOS Systems Inc., Waltham, MA
Murali Kudlugi , IKOS Systems Inc., Waltham, MA
pp. 2
Carl Ramey , Compaq Computer Corporation
Craig Barner , Compaq Computer Corporation
Scott Taylor , Compaq Computer Corporation
pp. 10
Session 1B: System-Level Exploration and Design
Tony Givargis , University of California, Irvine
J?rg Henkel , C&C Research Laboratories, NEC USA, Princeton, NJ
pp. 25
Todor Stefanov , Leiden Institute of Advanced, The Netherlands
Pieter van der Wolf , Philips Research Laboratories, The Netherlands
Paul Lieverse , Delft University of Technology, The Netherlands
pp. 31
William H. Mangione-Smith , University of California, Los Angeles
Wendong Hu , University of California, Los Angeles
pp. 39
Session 1C: Interconnect Planning
Amir H. Ajami , Univ. of Southern California, Los Angeles
Kaustav Banerjee , Stanford University, CA
Massoud Pedram , Univ. of Southern California, Los Angeles
pp. 44
Ruiqi Tian , University of Texas at Austin, TX
Hua Xiang , University of Texas at Austin, TX
D. F. Wong , University of Texas at Austin, TX
pp. 49
Bret Victor , University of California, Berkeley
Kurt Keutzer , University of California, Berkeley
pp. 57
Session 1D: Analog Macromodeling
Xuan Zeng , Fudan University, Shanghai, China
Dian Zhou , University of Texas at Dallas, Richardson, TX
Xieting Ling , Fudan University, Shanghai, China
pp. 65
Walter Daems , Katholieke Universiteit Leuven (Belgium)
Willy Sansen , Katholieke Universiteit Leuven (Belgium)
pp. 70
Session 3A: Sequential Synthesis
Sequential SPFDs (Abstract)
Subarnarekha Sinha , University of California at Berkeley
Andreas Kuehlmann , Cadence Berkeley Labs, Berkeley, CA
Robert K. Brayton , University of California at Berkeley
pp. 84
Luis Entrena , University Carlos III of Madrid
Enrique San Mill? , University Carlos III of Madrid
pp. 91
Ingmar Neumann , University of Frankfurt/Main, Germany
pp. 95
Nina Yevtushenko , Tomsk State University, Russia
Tiziano Villa , Via di S.Pantaleo, Italy
Robert K. Brayton , Univ. of California, Berkeley
Alex Petrenko , CRIM, Montreal, CAN
Alberto L. Sangiovanni-Vincentelli , Univ. of California, Berkeley
pp. 103
Session 3B: Compiler Techniques in System Level Design
Srinivas Devadas , Massachusetts Institute of Technology, Cambridge
Daniel Engels , Massachusetts Institute of Technology, Cambridge
Prabhat Jain , Massachusetts Institute of Technology, Cambridge
pp. 119
Seda Ogrenci-Memik , University of California, Los Angeles
Ryan Kastner , University of California, Los Angeles
Majid Sarrafzadeh , University of California, Los Angeles
pp. 127
Session 3C: Routing Architecture and Techniques for FPGAs
Ganapathy Parthasarathy , University of California, Santa Barbara
Amit Singh , University of California, Santa Barbara
pp. 132
Taewhan Kim , KAIST, Taejon, Korea
Nak-Woong Eum , Electronics & Telecom. Research Institute, Taejon Korea
pp. 137
Session 3D: Interconnect Performance and Reliability Optimization
Xianlong Hong , Tsinghua University, Beijing, China
Yici Cai , Tsinghua University, Beijing, China
C. K. Cheng , Univ. of California at San Diego
Jun Gu , Hong Kong Univ. of Science and Technology, Hong Kong
Wayne Dai , Univ. of California at Santa Cruz
pp. 153
Session 4A: Circuit Structure in Formal Verification
Jason Baumgartner , IBM Enterprise Systems Group, Austin, TX
pp. 176
Dominik Stoffel , University of Frankfurt/Main, Germany
pp. 183
Ying-Tsai Chang , University of California, Santa Barbara
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
pp. 190
Session 4B: System Level Power and Performance Modeling
C. Brandolese , Politecnico di Milano, Italy
W. Fornaciari , Politecnico di Milano, Italy
F. Salice , Politecnico di Milano, Italy
D. Sciuto , Politecnico di Milano, Italy
G. Beltrame , CEFRIEL, Milano, Italy
pp. 195
Mahmut Kandemir , Pennsylvania State University, PA
Ugur Sezer , University of Wisconsin, Madison
Victor Delaluz , Pennsylvania State University, PA
pp. 201
Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
Amit Nandi , Carnegie Mellon University, Pittsburgh, PA
Luciano Lavagno , Universita di' Udine, Italy
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
pp. 207
Session 4C: Topics in Physical Synthesis
Thomas Kutzschebauch , IBM TJ Watson Research Center, Yorktown Heights, NY
Leon Stok , IBM TJ Watson Research Center, Yorktown Heights, NY
pp. 216
Wilsin Gosti , University of California, Berkeley
Alberto L. Sangiovanni-Vincentelli , University of California, Berkeley
pp. 224
Xiaoping Tang , University of Texas at Austin, TX
D. F. Wong , University of Texas at Austin, TX
pp. 232
Session 4D: Model Order Reduction
Carlos P. Coelho , IST/Technical University of Lisbon, Lisboa, Portugal
L. Miguel Silveira , IST/Technical University of Lisbon, Lisboa, Portugal
pp. 245
Session 5A: Embedded Tutorial: Embedded Software and Systems
Niraj K. Jha , Princeton University, NJ
pp. 259
Lothar Thiele , Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
pp. 264
P. Yang , IMEC, Leuven, Belgium
C. Wong , IMEC, Leuven, Belgium
D. Verkest , IMEC, Leuven, Belgium
pp. 265
Session 5B: Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design
Domine Leenaerts , Philips Research, The Netherlands
Georges Gielen , Katholieke Universiteit Leuven, Belgium
Rob A. Rutenbar , Carnegie Mellon University, U.S.A
pp. 270
Session 6A: BDDs and SAT
Lintao Zhang , Princeton University
Matthew H. Moskewicz , UC Berkeley
Sharad Malik , Princeton University
pp. 279
Zijiang Yang , CCRL, NEC USA
Pranav Ashar , CCRL, NEC USA
Lintao Zhang , Princeton University
Aarti Gupta , CCRL, NEC USA
pp. 286
Edmund M. Clarke , Carnegie Mellon University, Pittsburgh, PA
Somesh Jha , University of Wisconsin, Madison, WI
Jim Kukula , Synopsys Inc., Beverton, OR
Tom Shiple , Synopsys Inc., Beverton, OR
Helmut Veith , TU Vienna, Austria
Dong Wang , Carnegie Mellon University, Pittsburgh, PA
pp. 293
Session 6B: Convergence of Abstractions in High-Level Synthesis
Armita Peymandoust , Stanford University, CA
pp. 300
Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA
Anoop Iyer , Carnegie Mellon University, Pittsburgh, PA
pp. 306
Anshuman Nayak , Mach Design Systems, Inc.
Alok Choudhary , Northwestern University
Malay Haldar , Mach Design Systems, Inc.
pp. 314
Jinyong Jung , Seoul National University, Korea
Sunghyun Lee , Seoul National University, Korea
Daehong Kim , Seoul National University, Korea
Kiyoung Choi , Seoul National University, Korea
pp. 320
Session 6C: Signal Integrity and Clock Design
James D. Z. Ma , University of Wisconsin, Madison
Lei He , University of Wisconsin, Madison
pp. 327
Haihua Su , University of Minnesota, Minneapolis
pp. 333
Yonghee Im , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 337
Session 6D: Analog Synthesis
H. Graeb , Technical University of Munich
S. Zizala , Infineon Technologies, Munich
J. Eckmueller , Infineon Technologies, Munich
K. Antreich , Technical University of Munich
pp. 343
Rodney Phelps , Carnegie Mellon University, Pittsburgh, PA
Michael J. Krasnicki , Texas Instruments Incorporated, Dallas, TX
Mark McClung , Texas Instruments Incorporated, Dallas, TX
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, PA
L. Richard Carley , Carnegie Mellon University, Pittsburgh, PA
pp. 350
G. Van der Plas , Katholieke Universiteit Leuven, Belgium
M. Steyaert , Katholieke Universiteit Leuven, Belgium
G. Gielen , Katholieke Universiteit Leuven, Belgium
W. Sansen , Katholieke Universiteit Leuven, Belgium
pp. 358
Session 7A: Manufacturing Test: Stuck-at to Crosstalk
Seiji Kajihara , Kyushu Institute of Technology, Japan
pp. 364
Irith Pomeranz , Purdue University , West Lafayette, IN
Chen Wang , University of Iowa, Iowa City
pp. 370
Seonki Kim , University of Minnesota, Minneapolis
Xiaoyun Sun , University of Minnesota, Minneapolis
pp. 375
Session 7B: Architecture Oriented Scheduling
Jianwen Zhu , University of Toronto, Ontario
pp. 380
Carlos Alba-Pinto , Eindhoven University of Technology
Bart Mesman , Philips Research Laboratories and Eindhoven Embedded Systems Institute
Jochen Jess , Eindhoven University of Technology
pp. 384
E. Bozorgzadeh , University of California, Los Angeles
R. Kastner , University of California, Los Angeles
M. Sarrafzadeh , University of California, Los Angeles
pp. 391
Session 7C: New Techniques in Routing
Fan Mo , University of California at Berkeley
Abdallah Tabbara , University of California at Berkeley
Robert K. Brayton , University of California at Berkeley
pp. 404
Andrew B. Kahng , UCSD, La Jolla, CA
Bao Liu , UCSD, La Jolla, CA
Ion Mandoiu , UCSD, La Jolla, CA
Alexander Zelikovsky , Georgia State University, Atlanta, GA
pp. 408
Session 7D: Issues in Substrate Coupling
Joe Kanapka , Massachusetts Institute of Technology, Cambridge
Jacob White , Massachusetts Institute of Technology, Cambridge
pp. 417
Minqing Liu , University of California, Santa Cruz
Tiejun Yu , Cadence Design Systems
Wayne W.-M. Dai , University of California, Santa Cruz
pp. 424
Session 8A: Combinational Optimization
Jan Hlavicka , Czech Technical University
Petr Fiser , Czech Technical University
pp. 439
Fadi A. Aloul , University of Michigan
Karem A. Sakallah , University of Michigan
pp. 443
Rupesh S. Shelar , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
pp. 449
Jennifer L. Wong , University of California, Los Angeles
Seapahn Meguerdichian , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 453
Session 8B: Real Time Scheduling and Performance Analysis
Amit Sinha , Massachusetts Institute of Technology, Cambridge
Anantha P. Chandrakasan , Massachusetts Institute of Technology, Cambridge
pp. 458
Hongchao (Stephanie) Liu , University of Notre Dame, IN
Xiaobo (Sharon) Hu , University of Notre Dame, IN
pp. 464
Felice Balarin , Cadence Berkeley Labs, Berkeley, CA
pp. 471
Session 8C: Power Analysis
Sani R. Nassif , IBM Austin Research Labs
Farid N. Najm , University of Toronto
pp. 480
J. L. Rossello , Balearic Islands University, Palma de Mallorca, Spain
Jaume Segura , Balearic Islands University, Palma de Mallorca, Spain
pp. 494
Session 8D: Timing and Noise Analysis
Jin-Fuw Lee , IBM T. J. Watson Research Center, Yorktown Heights, NY
D. L. Ostapko , IBM T. J. Watson Research Center, Yorktown Heights, NY
Jeffery Soreff , IBM Fishkill, Hopewell Junction, NY
C. K. Wong , The Chinese Univ. of Hong Kong, Shatin
pp. 507
Sergey Gavrilov , MicroStyle - Moscow, Russia
David Blaauw , University of Michigan
Supamas Sirichotiyakul , Motorola Inc. Austin, TX
Chanhee Oh , Motorola Inc. Austin, TX
Alexey Glebov , MicroStyle - Moscow, Russia
pp. 515
Session 9A: System Level Test and Reliability
Zebo Peng , Link?pings Universitet, Sweden
Erik Larsson , Link?pings Universitet, Sweden
pp. 523
Dhamin Al-Khalili , Royal Military College of Canada, Kingston, Ontario
C?me Rozon , Royal Military College of Canada, Kingston, Ontario
pp. 531
Session 9B: Power Issues in High Level Synthesis
Srivaths Ravi , NEC USA, Princeton, NJ
Anand Raghunathan , NEC USA, Princeton, NJ
Vijay Raghunathan , University of California, Los Angeles
pp. 545
Taewhan Kim , Korea Advanced Institute of Science & Technology, Taejon
Chun-Gi Lyuh , Korea Advanced Institute of Science & Technology, Taejon
pp. 553
Gang Qu , University of Maryland, College Park
pp. 560
Session 9C: Advances in Placement
Oluf Faroe , University of Copenhagen, Denmark
Martin Zachariasen , University of Copenhagen, Denmark
pp. 565
Ryan Kastner , University of California, Los Angeles
Majid Sarrafzadeh , University of California, Los Angeles
pp. 573
Prakash Gopalakrishnan , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 577
Session 9D: Interconnect Analysis and Extraction
Payam Heydari , University of California, Irvine
Massoud Pedram , University of Southern California, Los Angeles
pp. 586
Jingfang Huang , University of North Carolina, Chapel Hill
Ben Song , Massachusetts Institute of Technology, Cambridge
Zhenhai Zhu , Massachusetts Institute of Technology, Cambridge
pp. 592
Steven C. Chan , Cadence Design Systems, Inc.
K. L. Shepard , Columbia University, New York
pp. 598
Session 10A: Don't Care Optimization and Boolean Matching
Chih-Wei (Jim) Chang , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 606
R. K. Brayton , University of California, Berkeley
pp. 618
Session 10B: Power Saving Techniques for Embedded Processors
Oliver Schliebusch , Integrated Signal Processing Systems, RWTH Aachen, Germany
Achim Nohl , Integrated Signal Processing Systems, RWTH Aachen, Germany
Gunnar Braun , Integrated Signal Processing Systems, RWTH Aachen, Germany
Oliver Wahlen , Integrated Signal Processing Systems, RWTH Aachen, Germany
Heinrich Meyr , Integrated Signal Processing Systems, RWTH Aachen, Germany
pp. 625
Mahesh Mehendale , Texas Instruments India Ltd., Bangalore, India
Subash G Chandar , Texas Instruments India Ltd., Bangalore, India
pp. 631
Sri Parameswaran , The University of New South Wales, Kensington
J? Henkel , NEC USA Inc., Princeton, NJ
pp. 635
Session 10C: Embedded Tutorial: IC Power Distribution Challenges
Sudhakar Bobba , Sun Microsystems, Inc.
Tyler Thorp , Sun Microsystems, Inc.
Kathirgamar Aingaran , Afara Websystems
Dean Liu , Sun Microsystems, Inc.
pp. 643
Shen Lin , Apache Design Solutions, Inc., Palo Alto, CA
Norman Chang , Apache Design Solutions, Inc., Palo Alto, CA
pp. 651
Session 11A: Panel: Automatic Hierarchical Design: Fantasy or Reality?
Author Index (PDF)
pp. 657
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