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Computer-Aided Design, International Conference on (2000)
San Jose, California
Nov. 5, 2000 to Nov. 9, 2000
ISBN: 0-7803-6445-7
TABLE OF CONTENTS
Introduction
Foreword (PDF)
pp. iii
Reviewers (PDF)
pp. xvii
Keynote (PDF)
pp. xxi
Session 1A: Floorplanning and Partitioning
Xianlong Hong , Tsinghua University, Beijing, China
Gang Huang , Tsinghua University, Beijing, China
Yici Cai , Tsinghua University, Beijing, China
Jiangchun Gu , Tsinghua University, Beijing, China
Sheqin Dong , Tsinghua University, Beijing, China
Chung-Kuan Cheng , University of California, San Diego
Jun Gu , University of Hong Kong
pp. 8
Florin Balasa , University of Illinois at Chicago
pp. 13
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
Stefanus Mantik , UCLA Computer Science Dept., Los Angeles, CA
pp. 17
Session 1B: High Level Simulation
Peter M. Maurer , Univ. of South Florida, Tampa
pp. 23
Gernot Koch , Synopsys Inc., Mountain View, CA
Taewhan Kim , KAIST, Korea
Reiner Genevriere , Synopsys Inc., Mountain View, CA
pp. 33
Session 1C: Methods for DSP Synthesis and Debugging
Farinaz Koushanfar , University of California, Los Angeles
Darko Kirovski , Microsoft Research, Redmond, WA
Miodrag Potkonjak , University of California, Los Angeles
pp. 40
Per Gunnar Kjeldsberg , Norwegian University of Science and Technology, Trondheim, Norway
Francky Catthoor , IMEC, Leuven, Belgium, also at Katholieke Universiteit Leuven
Einar J. Aas , Norwegian University of Science and Technology, Trondheim, Norway
pp. 44
Hyeong-Ju Kang , Korea Advanced Institute of Science and Technology, Korea
Hansoo Kim , Korea Advanced Institute of Science and Technology, Korea
In-Cheol Park , Korea Advanced Institute of Science and Technology, Korea
pp. 51
Session 1D: Issues in Timing Estimation
Yu Cao , UC Berkeley, USA
Chenming Hu , UC Berkeley, USA
Xuejue Huang , UC Berkeley, USA
Andrew B. Kahng , UCLA, USA
Sudhakar Muddu , Silicon Graphics, Inc., USA
Dirk Stroobandt , Ghent University, Belgium
Dennis Sylvester , Synopsys, Inc., USA
pp. 56
Michael Orshansky , University of California, Berkeley
Linda Milor , eSilicon Corporation, Berkeley, CA
Pinhong Chen , University of California, Berkeley
Kurt Keutzer , University of California, Berkeley
Chenming Hu , University of California, Berkeley
pp. 62
Pinhong Chen , U. C. Berkeley
Desmond A. Kirkpatrick , Intel Corp., Hillsboro, OR
Kurt Keutzer , U. C. Berkeley
pp. 68
Session 2A: Embedded Tutorial
Jan M. Rabaey , University of California, Berkeley
Miodrag Potkonjak , University of California, Los Angeles
Farinaz Koushanfar , University of California, Los Angeles
Suet-Fei Li , University of California, Berkeley
Tim Tuan , University of California, Berkeley
pp. 76
Session 2B: Embedded Tutorial
Ralph H. J. M. Otten , Eindhoven University of Technology, The Netherlands
Paul Stravers , Philips Research, The Netherlands
pp. 84
Session 3A: Topics in Routing
Hongbing Fan , University of Victoria
Jiping Liu , University of Lethbridge
Yu-Liang Wu , Chinese University of Hong Kong
pp. 93
Jiang Hu , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
pp. 99
Feodor F. Dragan , UCLA Department of Computer Science, Los Angeles
Andrew B. Kahng , UCLA Department of Computer Science, Los Angeles
Ion Mandoiu , Georgia Institute of Technology, Atlanta
Sudhakar Muddu , Silicon Graphics, Inc., Mountain View, CA
Alexander Zelikovsky , Georgia State University, Atlanta
pp. 104
Predictable Routing (Abstract)
Ryan Kastner , Northwestern University, Evanston, IL
Elaheh Bozorgzadeh , Northwestern University, Evanston, IL
Majid Sarrafzadeh , Northwestern University, Evanston, IL
pp. 110
Session 3B: Partial Verification Techniques
Pei-Hsin Ho , Advanced Technology Group, Synopsys Inc.
Thomas Shiple , Advanced Technology Group, Synopsys Inc.
Kevin Harer , Advanced Technology Group, Synopsys Inc.
James Kukula , Advanced Technology Group, Synopsys Inc.
Robert Damiano , Advanced Technology Group, Synopsys Inc.
Valeria Bertacco , Advanced Technology Group, Synopsys Inc.
Jerry Taylor , Advanced Technology Group, Synopsys Inc.
Jiang Long , Advanced Technology Group, Synopsys Inc.
pp. 120
C. Norris Ip , Cadence Berkeley Labs, California
pp. 127
Session 3C: Scheduling and Compilation for Embedded Systems
Dirk Ziegenbein , TU Braunschweig
Jan Uerpmann , TU Braunschweig
Rolf Ernst , TU Braunschweig
pp. 135
Session 3D: Inductance and Full-Wave Analysis
K. L. Shepard , Columbia University, New York, NY
D. Sitaram , Columbia University, New York, NY
Yu Zheng , Columbia University, New York, NY
pp. 142
Anirudh Devgan , IBM Microelectronics, Austin, TX
Hao Ji , UC Santa Cruz CE Dept.
Wayne Dai , UC Santa Cruz CE Dept.
pp. 150
Charlie C.-P. Chen , University of Wisconsin-Madison
Tae-Woo Lee , University of Wisconsin-Madison
Narayanan Murugesan , University of Wisconsin-Madison
Susan C. Hagness , University of Wisconsin-Madison
pp. 156
Session 4A: Placement I
Sung-Woo Hur , University of Illinois at Chicago
John Lillis , University of Illinois at Chicago
pp. 165
Fan Mo , University of California, Berkeley
Abdallah Tabbara , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
pp. 177
Session 4B: High-Level Design Tools for Analog Circuits
Jeongjin Roh , The University of Texas at Austin
Suresh Seshadri , The University of Texas at Austin
Jacob A. Abraham , The University of Texas at Austin
pp. 182
K. Francken , Katholieke Universiteit Leuven
P. Vancorenland , Katholieke Universiteit Leuven
G. Gielen , Katholieke Universiteit Leuven
pp. 188
Erik Lauwers , Katholieke Universiteit Leuven
Georges Gielen , Katholieke Universiteit Leuven
pp. 193
Session 4C: Delay Budgeting and Distribution
Chunhong Chen , Northwestern University, Evanston, IL
Xiaojian Yang , Northwestern University, Evanston, IL
Majid Sarrafzadeh , Northwestern University, Evanston, IL
pp. 198
Chien-Chu Kuo , Tsing Hua University, Hsinchu, Taiwan
Allen C.-H. Wu , Tsing Hua University, Hsinchu, Taiwan
pp. 202
Rongtian Zhang , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
David B. Janes , Purdue University, West Lafayette, IN
pp. 208
Session 4D: Interconnect Analysis
Michael Beattie , Carnegie Mellon University, Pittsburgh, PA
Satrajit Gupta , Carnegie Mellon University, Pittsburgh, PA
Lawrence Pileggi , Carnegie Mellon University, Pittsburgh, PA
pp. 215
Xiaodong Yang , U.C. San Diego
Chung-Kuan Cheng , U.C. San Diego
Walter H. Ku , U.C. San Diego
Robert J. Carragher , Fujitsu Laboratories of America
pp. 222
Chandramouli V. Kashyap , IBM Corp., Austin, TX
Charles J. Alpert , IBM Corp., Austin, TX
Anirudh Devgan , IBM Corp., Austin, TX
pp. 229
Session 5A: Embedded Tutorial
Incremental CAD (Abstract)
Olivier Coudert , Monterey Design Systems, Sunnyvale, CA
Jason Cong , University of California, Los Angeles
Sharad Malik , Princeton University, NJ
Majid Sarrafzadeh , Northwestern University, Evanston, IL
pp. 236
Session 5B: Embedded Tutorial
Thomas A. Henzinger , University of California, Berkeley
Shaz Qadeer , Compaq Systems Research Center
Sriram K. Rajamani , Microsoft Research
pp. 245
Session 6A: Placement II
Ke Zhong , University of Illinois-Chicago
Shantanu Dutt , University of Illinois-Chicago
pp. 254
Maogang Wang , Northwestern University, Evan ston, IL
Xiaojian Yang , Northwestern University, Evan ston, IL
Majid Sarrafzadeh , Northwestern University, Evan ston, IL
pp. 260
Terry Tao Ye , Stanford University, CA
Giovanni De Micheli , Stanford University, CA
pp. 264
Session 6B: Analog and RF Simulation
Amit Mehrotra , Univerity of Illinois at Urbana-Champaign
pp. 277
Alper Demir , Bell Laboratories, Murray Hill, New Jersey
David Long , Bell Laboratories, Murray Hill, New Jersey
Jaijeet Roychowdhury , Bell Laboratories, Murray Hill, New Jersey
pp. 283
Session 6C: Markovian Analysis and Asynchronous Circuits
Alper Demir , Bell Laboratories, Murray Hill, NJ
Peter Feldmann , Bell Laboratories, Murray Hill, NJ
pp. 290
Sangyun Kim , University of Southern California, Los Angeles
Peter A. Beerel , University of Southern California, Los Angeles
pp. 296
Session 6D: Low Power Interconnect Modeling and Optimization
Ki-Wook Kim , Univ. of Illinois at Urbana-Champaign, USA
Kwang-Hyun Baek , Univ. of Illinois at Urbana-Champaign, USA
Naresh Shanbhag , Univ. of Illinois at Urbana-Champaign, USA
C. L. Liu , National Tsing Hua University, Taiwan
Sung-Mo Kang , Univ. of Illinois at Urbana-Champaign, USA
pp. 318
Paul P. Sotiriadis , Massachusetts Institute of Technology, Cambridge
Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge
pp. 322
Session 7A: Panel
A. Richard Newton , Univ. of California, Berkeley
pp. 329
Session 8A: Static Timing Analysis
David Blaauw , Motorola Inc. Austin, TX
Vladimir Zolotov , Motorola Inc. Austin, TX
Savithri Sundareswaran , Motorola India Electronics Ltd., Bangalore, India
Chanhee Oh , Motorola Inc. Austin, TX
Rajendran Panda , Motorola Inc. Austin, TX
pp. 338
Pawan Kulshreshtha , Cadence Design Systems Inc., San Jose, CA
Robert Palermo , Cadence Design Systems Inc., San Jose, CA
Mohammad Mortazavi , Cadence Design Systems Inc., San Jose, CA
Cyrus Bamji , Canesta Inc., Santa Clara, CA
Hakan Yalcin , Cadence Design Systems Inc., San Jose, CA
pp. 344
Session 8B: Embedded Systems Power Management and Validation
Dinesh Ramanathan , University of California, Irvine
Sandy Irani , University of California, Irvine
Rajesh Gupta , University of California, Irvine
pp. 350
Youngsoo Shin , University of Tokyo, Japan
Kiyoung Choi , Seoul National University, Korea
Takayasu Sakurai , University of Tokyo, Japan
pp. 365
Qiushuang Zhang , University of Massachusetts, Amherst
Ian G. Harris , University of Massachusetts, Amherst
pp. 369
Session 8C: Advances in Layout and Synthesis
Wei Chen , University of Southern California, Los Angeles
Cheng-Ta Hsieh , Verplex Systems, Inc., Milpitas, CA
Massoud Pedram , University of Southern California, Los Angeles
pp. 374
Rajeev Murgai , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
pp. 379
Ching-Hwa Cheng , National Chung Cheng University, Chiayi, Taiwan
Shih-Chieh Chang , National Chung Cheng University, Chiayi, Taiwan
Shin-De Li , National Chung Cheng University, Chiayi, Taiwan
Wen-Ben Jone , National Chung Cheng University, Chiayi, Taiwan
Jinn-Shyan Wang , National Chung Cheng University, Chiayi, Taiwan
pp. 387
Session 8D: Embedded Tutorial
Yervant Zorian , LogicVision Inc., San Jose, CA
Sujit Dey , University of California at San Diego, La Jolla
Michael J. Rodgers , Intel Corp., Santa Clara, CA
pp. 392
Session 9A: Noise and Performance Issues in Routing
Chung-Wen Albert Tsao , Ultima Interconnect Technology, Sunnyvale, CA
Cheng-Kok Koh , ECE, Purdue University, West Lafayette, IN
pp. 400
Guoan Zhong , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 406
Session 9B: Communication Architectures Design and Analysis
Milenko Drinic , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
Seapahn Meguerdichian , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 420
Kanishka Lahiri , UC San Diego
Anand Raghunathan , NEC USA C&C Research Labs, Princeton, NJ
Sujit Dey , UC San Diego
pp. 424
Peter Grun , University of California, Irvine
Nikil Dutt , University of California, Irvine
Alex Nicolau , University of California, Irvine
pp. 431
Session 9C: Performance Driven Logic Synthesis
Thomas Kutzschebauch , IBM TJ Watson Research Center, Yorktown Heights, NY
Leon Stok , IBM TJ Watson Research Center, Yorktown Heights, NY
pp. 439
Ankur Srivastava , Northwestern University, Evanston, Illinois
Ryan Kastner , Northwestern University, Evanston, Illinois
Majid Sarrafzadeh , Northwestern University, Evanston, Illinois
pp. 447
Arlindo L. Oliveira , Cadence European Labs./IST-INESC, Lisboa, Portugal
Rajeev Murgai , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
pp. 451
Session 9D: New Approaches to At-Speed BIST and Diagnosis
Y. Huang , University of Iowa, Iowa City
I. Pomeranz , Purdue University, West Lafayette, IN
S. M. Reddy , University of Iowa, Iowa City
J. Rajski , Mentor Graphics Corporation, Wilsonville, OR
pp. 459
Seonki Kim , University of Minnesota, Minneapolis
Bapiraju Vinnakota , University of Minnesota, Minneapolis
pp. 464
Chi-Feng Wu , National Tsing Hua University, Hsinchu, Taiwan
Chih-Tsun Huang , National Tsing Hua University, Hsinchu, Taiwan
Chih-Wea Wang , National Tsing Hua University, Hsinchu, Taiwan
Kuo-Liang Cheng , National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
pp. 468
Ian Harris , University of Massachusetts at Amherst
Russell Tessier , University of Massachusetts at Amherst
pp. 472
Session 10A: Power Analysis and Optimization
G. Bai , University of Illinois at Urbana-Champaign
S. Bobba , University of Illinois at Urbana-Champaign
I. N. Hajj , University of Illinois at Urbana-Champaign
pp. 481
Shiyou Zhao , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
pp. 487
Jing-Jia Liou , University of California, Santa Barbara
Angela Krstic , University of California, Santa Barbara
Yi-Min Jiang , Synopsys Inc., Mountain View, CA
Kwang-Ting Cheng , University of California, Santa Barbara
pp. 493
Session 10B: VLIW Exploration and Design Synthesis
Mariagiovanna Sami , Politecnico di Milano, Italy
Donatella Sciuto , Politecnico di Milano, Italy
Cristina Silvano , Politecnico di Milano, Italy
Vittorio Zaccaria , Politecnico di Milano, Italy
pp. 498
Margarida F. Jacome , University of Texas, Austin, TX
Gustavo de Veciana , University of Texas, Austin, TX
Viktor Lapinskii , University of Texas, Austin, TX
pp. 504
James C. Hoe , Carnegie Mellon University
Arvind , Massachusetts Institute of Technology
pp. 511
Session 10C: Flexibility in Logic Synthesis
Yunjian Jiang , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
pp. 520
Victor N. Kravets , University of Michigan, Ann Arbor
Karem A. Sakallah , University of Michigan, Ann Arbor
pp. 526
Shih-Chieh Chang , National Chung-Cheng University, Chia-Yi, Taiwan
Zhong-Zhen Wu , National Chung-Cheng University, Chia-Yi, Taiwan
He-Zhe Yu , National Chung-Cheng University, Chia-Yi, Taiwan
pp. 533
Session 10D: Digital and Analog Test Generation
Ilker Hamzaoglu , Motorola Labs, Schaumburg, IL
Janak H. Patel , University of Illinois, Urbana, IL
pp. 538
Irith Pomeranz , University of Iowa, Iowa City
Sudhakar M. Reddy , University of Iowa, Iowa City
pp. 544
Tomoo Inoue , Hiroshima City University, Japan
Debesh Kumar Das , Jadavpur University, India
Chiiho Sano , Nara Institute of Science and Technology, Japan
Takahiro Mihara , Mitsubishi Electronic Control Software Corporation, Japan
Hideo Fujiwara , Nara Institute of Science and Technology, Japan
pp. 550
M. Pronath , Technical University of Munich
V. Gloeckel , Technical University of Munich
H. Graeb , Technical University of Munich
pp. 557
Sudip Chakrabarti , Georgia Institute of Technology, Atlanta
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
pp. 562
Session 11A: Embedded Tutorial
Session 11B: Embedded Tutorial
Andrzej J. Strojwas , Carnegie Mellon University, Pittsburgh & PDF Solutions, Inc., San Jose, CA
pp. 575
Author Index (PDF)
pp. 576
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