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1999 International Conference on Computer-Aided Design (ICCAD '99)
San Jose, CA
November 07-November 11
ISBN: 0-7803-5832-5
Table of Contents
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Session 1A: Sequential and Datapath Optimization
Vijay Sundararajan, University of Minnesota, Minneapolis
Sachin S. Sapatnekar, University of Minnesota, Minneapolis
Keshab K. Parhi, University of Minnesota, Minneapolis
pp. 2
Kei-Yong Khoo, University of California, Los Angeles
Zhan Yu, University of California, Los Angeles
Alan N. Willson, Jr., University of California, Los Angeles
pp. 14
Session 1B: Placement I
Hussein Etawil, University of Waterloo, Ontario
Shawki Areibi, University of Waterloo, Ontario
Anthony Vannelli, University of Waterloo, Ontario
pp. 20
Ingmar Neumann, J.W.G. University Frankfurt a.M, Germany
Dominik Stoffel, J.W.G. University Frankfurt a.M, Germany
Hendrik Hartje, University of Potsdam, Germany
Wolfgang Kunz, J.W.G. University Frankfurt a.M, Germany
pp. 25
Jinan Lou, University of Southern California, Los Angeles
Wei Chen, University of Southern California, Los Angeles
Massoud Pedram, University of Southern California, Los Angeles
pp. 31
Session 1C: BDDs in Formal Verification
Aiguo Xie, University of Southern California, Los Angeles
Peter A. Beerel, University of Southern California, Los Angeles
pp. 37
In-Ho Moon, University of Colorado at Boulder
James Kukula, Advanced Technology Group, Synopsys Inc.
Tom Shiple, Advanced Technology Group, Synopsys Inc.
Fabio Somenzi, University of Colorado at Boulder
pp. 41
Hiroyuki Higuchi, Fujitsu Laboratories Ltd., Kawasaki, Japan
Fabio Somenzi, University of Colorado, Boulder
pp. 45
Session 1D: Analog and Mixed-Signal
M. Gourary, IPPM, Russian Academy of Sciences, Moscow
S. Ulyanov, IPPM, Russian Academy of Sciences, Moscow
M. Zharov, IPPM, Russian Academy of Sciences, Moscow
S. Rusakov, IPPM, Russian Academy of Sciences, Moscow
K. Gullapalli, Motorola Inc., Austin, Texas
B. Mulvaney, Motorola Inc., Austin, Texas
pp. 61
Maria del Mar Hershenson, Stanford University
Ali Hajimiri, California Institue of Technology
Sunderarajan S. Mohan, Stanford University
Stephen P. Boyd, Stanford University
Thomas H. Lee, Stanford University
pp. 65
Alper Demir, Bell Laboratories, Murray Hill, New Jersey
Peter Feldmann, Bell Laboratories, Murray Hill, New Jersey
pp. 70
Session 2A: Power Optimization
Shanq-Jang Ruan, National Taiwan University, Taipei
Rung-Ji Shang, National Taiwan University, Taipei
Feipei Lai, National Taiwan University, Taipei
Shyh-Jong Chen, National Taiwan University, Taipei
Xian-Jun Huang, National Taiwan University, Taipei
pp. 84
Session 2B: Placement II
Serkan Askar, University of Massachusetts, Amherst
Maciej Ciesielski, University of Massachusetts, Amherst
pp. 98
Session 2C: Domino- and ATPG-Based Logic Synthesis
Ki-Wook Kim, University of Illinois at Urbana-Champaign
C. L. Liu, National Tsing Hua University
Sung-Mo Kang, University of Illinois at Urbana-Champaign
pp. 111
Shih-Chieh Chang, National Chung-Cheng University, Jay-Yi, Taiwan
Jung-Cheng Chuang, National Chung-Cheng University, Jay-Yi, Taiwan
Zhong-Zhen Wu, National Chung-Cheng University, Jay-Yi, Taiwan
pp. 115
Session 2D: Electrical and Thermal Analysis
Tuyen V. Nguyen, IBM Austin Research Laboratory, TX
Peter O'Brien, IBM EDA, Austin, TX
David Winston, IBM EDA, Hopewell Junction, NY
pp. 120
Anil Samavedam, Silicon Laboratories Inc., Austin, TX
Karti Mayaram, Washington State University, Pullman, WA
Terri Fiez, Oregon State University, Corvallis, OR
pp. 128
Pinhong Chen, Univ. of California at Berkeley
Kurt Keutzer, Univ. of California at Berkeley
pp. 132
Session 3A: Automatic Test Pattern Generation
Fatih Kocan, Case Western Reserve University, Cleveland, Ohio
Daniel G. Saab, Case Western Reserve University, Cleveland, Ohio
pp. 152
Session 3B: Routing
Ion I. Mandoiu, Georgia Institute of Technology, Atlanta
Vijay V. Vazirani, Georgia Institute of Technology, Atlanta
Joseph L. Ganley, Simplex Solutions, Inc., Sunnyvale, CA
pp. 157
Yu Chen, UCLA Department of Computer Science, Los Angeles, CA
Andrew B. Kahng, UCLA Department of Computer Science, Los Angeles, CA
Gang Qu, UCLA Department of Computer Science, Los Angeles, CA
Alexander Zelikovsky, Georgia State University, Atlanta
pp. 168
Session 3C: Logic-Level Performance Optimization
David S. Kung, IBM T. J. Watson Research Center, Yorktown Heights, NY
Ruchir Puri, IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 178
Session 3D: Practical Issues in Order Reduction
Xiaodong Yang, University of California, San Diego
Walter H. Ku, University of California, San Diego
Chung-Kuan Cheng, University of California, San Diego
pp. 208
Altan Odabasioglu, Monterey Design Systems, Inc., Sunnyvale, CA
Mustafa Celik, Monterey Design Systems, Inc., Sunnyvale, CA
Lawrence T. Pileggi, Carnegie Mellon University, Pittsburgh, PA
pp. 214
Session 4A: Embedded Tutorial
Session 4B: Embedded Tutorial
Mattan Kamon, Microcosm Technologies, Inc, Cambridge, Ma
Steve McCormick, Sapphire Design Automation, Santa Clara, CA
Ken Shepard, Columbia University, New York, NY
pp. 223
Session 5A: Timing Optimization
C. Albrecht, University of Bonn, Germany
B. Korte, University of Bonn, Germany
J. Schietke, University of Bonn, Germany
J. Vygen, University of Bonn, Germany
pp. 232
Chandu Visweswariah, IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Andrew R. Conn, IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 244
Session 5B: Compilation Techniques for Embedded Systems
Session 5C: High Level Power Exploration
Tony D. Givargis, University of California, Riverside
J? Henkel, NEC USA, Princeton, NJ
Frank Vahid, University of California, Riverside
pp. 270
Eui-Young Chung, Stanford University, CA
Luca Benini, Universit? di Bologna, Italy
Giovanni De Micheli, Stanford University, CA
pp. 274
Alessandro Bogliolo, Universit? di Bologna, Italy
Roberto Corgnati, Politecnico di Torini, Italy
Enrico Macii, Politecnico di Torini, Italy
Massimo Poncino, Politecnico di Torini, Italy
pp. 284
Session 5D: Analog and Mixed Signal Test
Arani Sinha, University of Southern California, Los Angeles
Sandeep K. Gupta, University of Southern California, Los Angeles
Melvin A. Breuer, University of Southern California, Los Angeles
pp. 289
Michael Cuviello, University of California, San Diego
Sujit Dey, University of California, San Diego
Xiaoliang Bai, University of California, San Diego
Yi Zhao, University of California, San Diego
pp. 297
Alfred V. Gomes, Georgia Institute of Technology, Atlanta
Abhijit Chatterjee, Georgia Institute of Technology, Atlanta
pp. 304
Session 6A: Globally Untimed Locally Timed Design
Luca P. Carloni, University of California at Berkeley
Kenneth L. McMillan, Cadence Berkeley Laboratories
Alexander Saldanha, Cadence Berkeley Laboratories
Alberto L. Sangiovanni-Vincentelli, University of California at Berkeley
pp. 309
Hiroshi Saito, Univ. of Aizu, Japan
Alex Kondratyev, Univ. of Aizu, Japan
Jordi Cortadella, Univ. Polit?cnica, Catalunya, Spain
Luciano Lavagno, Univ. of Udine, Italy
Alexander Yakovlev, Univ. of Newcastle upon Tyne, UK
pp. 316
Jordi Cortadella, Univ. Polit?cnica de Catalunya, Barcelona, Spain
Michael Kishinevsky, Strategic CAD Lab, Intel Corporation, USA
Steven M. Burns, Strategic CAD Lab, Intel Corporation, USA
Ken Stevens, Strategic CAD Lab, Intel Corporation, USA
pp. 324
Sung Tae Jung, University of Utah, Salt Lake City
Chris J. Myers, University of Utah, Salt Lake City
pp. 332
Session 6B: Task-Level Analysis and Synthesis
Session 6C: Floorplanning and Partitioning
Hung-Ming Chen, University of Texas at Austin, TX
Hai Zhou, University of Texas at Austin, TX
F. Y. Young, University of Texas at Austin, TX
D. F. Wong, University of Texas at Austin, TX
Hannah H. Yang, Intel Corporation, Hillsboro, OR
Naveed Sherwani, Intel Corporation, Hillsboro, OR
pp. 354
Jason Cong, University of California, Los Angeles
Tianming Kong, University of California, Los Angeles
David Zhigang Pan, University of California, Los Angeles
pp. 358
Mango Chia-Tso Chao, National Chiao Tung University, Hsinchu, Taiwan
Guang-Ming Wu, National Chiao Tung University, Hsinchu, Taiwan
Iris Hui-Ru Jiang, National Chiao Tung University, Hsinchu, Taiwan
Yao-Wen Chang, National Chiao Tung University, Hsinchu, Taiwan
pp. 364
Session 6D: Advances in Model Order Reduction
Janet M. Wang, University of California at Berkeley
Ernest S. Kuh, University of California at Berkeley
Qingjian Yu, University of California at Berkeley
pp. 370
Emad Gad, Carleton University, Ottawa, Canada
Michel Nakhla, Carleton University, Ottawa, Canada
pp. 376
Jing-Rebecca Li, Massachusetts Institute of Technology, Cambridge
Jacob White, Massachusetts Institute of Technology, Cambridge
pp. 380
Session 7A: Core Test
Srivaths Ravi, Princeton University, NJ
Ganesh Lakshminarayana, NEC USA, Inc., Princeton, NJ
Niraj K. Jha, Princeton University, NJ
pp. 385
Qiushuang Zhang, University of Massachusetts at Amherst
Ian Harris, University of Massachusetts at Amherst
pp. 395
Session 7B: Graph Techniques for Design Optimization
Inki Hong, Synopsys Inc., Mountain View, CA
Miodrag Potkonjak, University of California, Los Angeles
Lisa M. Guerra, Rockwell Semiconductor, Newport Beach, CA
pp. 406
Junhyung Um, Korea Adv. Institute of Science & Technology, Taejon, Korea
Taewhan Kim, Korea Adv. Institute of Science & Technology, Taejon, Korea
C. L. Liu, National Tsing Hua Univ., Hsinchu, Taiwan
pp. 410
Session 7C: Interconnect
Yehea I. Ismail, University of Rochester, New York
Eby G. Friedman, University of Rochester, New York
Jose L. Neves, IBM Microelectronics, East Fishkill, New York
pp. 420
Ron Ho, Stanford University, CA
Ken Mai, Stanford University, CA
Hema Kapadia, Stanford University, CA
Mark Horowitz, Stanford University, CA
pp. 425
Charles J. Alpert, IBM Austin Research Laboratory, TX
Anirudh Devgan, IBM Server Group, Austin, TX
Stephen T. Quay, IBM Server Group, Austin, TX
pp. 430
Session 7D: Techniques for Parasitic Extraction
A. J. Dammers, Netherlands Institute for Metals Research and Delft University of Technology
N. P. van der Meijs, Delft University of Technology
pp. 445
Session 8A: Embedded Tutorial
Session 8B: Embedded Tutorial
Session 9A: Test Pattern Analysis
Session 9B: Memory and Interconnect Optimization in High Level Synthesis
Dirk Herrmann, Technische Universit?t Braunschweig, Germany
Rolf Ernst, Technische Universit?t Braunschweig, Germany
pp. 489
Session 9C: System Verification
Thomas A. Henzinger, University of California at Berkeley
Xiaojun Liu, University of California at Berkeley
Shaz Qadeer, University of California at Berkeley
Sriram K. Rajamani, University of California at Berkeley
pp. 494
Harry Hsieh, University of California, Berkeley
Alberto Sangiovanni-Vincentelli, University of California, Berkeley
Felice Balarin, Cadence Design Systems
Luciano Lavagno, Cadence Design Systems
pp. 505
Session 9D: Fanout Optimization
Rajeev Murgai, Fujitsu Laboratories of America, Inc., Sunnyvale, CA
pp. 511
Peyman Rezvani, University of Southern California, Los Angeles
Amir H. Ajami, University of Southern California, Los Angeles
Massoud Pedram, University of Southern California, Los Angeles
Hamid Savoj, Magma Design Automation, Inc., Cupertino, CA
pp. 516
Session 10A: Timing Analysis
Clayton B. McDonald, Carnegie Mellon University, Pittsburgh, PA
Randal E. Bryant, Carnegie Mellon University, Pittsburgh, PA
pp. 526
Yuji Kukimoto, Monterey Design Systems, Inc., Sunnyvale, CA
Robert K. Brayton, University of California, Berkeley
pp. 544
Session 10B: Concurrency in Embedded Systems
L. Thiele, Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
K. Strehl, Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
D. Ziegenbein, Technical University of Braunschweig, Braunschweig, Germany
R. Ernst, Technical University of Braunschweig, Braunschweig, Germany
J. Teich, University of Paderborn, Germany
pp. 558
Session 10C: Semi-Formal Verification
Andreas Kuehlmann, IBM T. J. Watson Research Center, Yorktown Heights, NY
Kenneth L. McMillan, Cadence Design Systems, Berkeley, CA
Robert K. Brayton, University of California at Berkeley
pp. 574
Jun Yuan, Motorola Inc., Austin, TX
Kurt Shultz, Motorola Inc., Austin, TX
Carl Pixley, Motorola Inc., Austin, TX
Hillel Miller, Motorola Inc., Herzelia, Israel
Adnan Aziz, University of Texas at Austin
pp. 584
Session 10D: Intellectual Property Protection
Edoardo Charbon, Cadence Design Systems, San Jose, CA
Ilhami Torunoglu, Cadence Design Systems, San Jose, CA
pp. 591
Andrew B. Kahng, UCLA Computer Science Dept., Los Angeles, CA
Darko Kirovski, UCLA Computer Science Dept., Los Angeles, CA
Stefanus Mantik, UCLA Computer Science Dept., Los Angeles, CA
Miodrag Potkonjak, UCLA Computer Science Dept., Los Angeles, CA
Jennifer L. Wong, UCLA Computer Science Dept., Los Angeles, CA
pp. 600
Session 11A: Embedded Tutorial
Session 11B: ICCAD/ISSS Invited Papers
Session 12A: Embedded Tutorial
Session 12B: Joint ICCAD / ISSS Session
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