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1998 International Conference on Computer-Aided Design (ICCAD '98)
San Jose, California, United States
November 08-November 12
ISBN: 1-58113-008-2
Table of Contents
Tutorial 1: Embedded Memories in systems Design - from Technology to Systems Architecture
Tutorial 2: Real-Time Operating Systems for Embedded Computing
Tutorial 3: High-Level Design Validation and Test
Tutorial 4: Interconnect in High Speed Designs: Problems, Methodologies and Tools
Panel: How Will CAD Handle Billion-Transistor Systems?
Session 1A: Topics in Circuit Simulation
Ali Sadigh, IBM Electronic Design Automation, HopeweIl Junction, NY
Anirudh Devgan, IBM Austin Research Laboratory, Austin, TX
Tuyen V. Nguyen, IBM Austin Research Laboratory, Austin, TX
pp. 12-18
Lawrence Pileggi, Carnegie Mellon University, Pittsburgh, PA
Emrah Acar, Carnegie Mellon University, Pittsburgh, PA
Tao Lin, Carnegie Mellon University, Pittsburgh, PA
pp. 19-25
Session 1B: Layout and Logic Synthesis
Alberto L. Sangiovanni-Vincentelli, University of California Berkeley, CA
Amit Narayan, Monterey Design Systems, Sunnyvale, CA
Robert K. Brayton, University of California Berkeley, CA
Wilsin Gosti, University of California Berkeley, CA
pp. 26-33
Jai-Ming Lin, National Chiao Tung University, Hsinchu, Taiwan
D. F. Wong, University of Texas at Austin
Yao-Wen Chang, National Chiao Tung University, Hsinchu, Taiwan
pp. 34-39
Songjie Xu, University of California, Los Angeles
Jason Cong, University of California, Los Angeles
pp. 40-44
Session 1C: Dynamic System Synthesis
Ken Hines, University of Washington, Seattle
Kurt Partidge, University of Washington, Seattle
Gaetano Borriello, University of Washington, Seattle
Pai Chou, University of Washington, Seattle
pp. 46-53
J. Teich, ETH Z?
K. Richter, TU Braunschweig
L. Thiele, ETH Z?
R. Ernst, TU Braunschweig
D. Ziegenbein, TU Braunschweig
pp. 54-61
Session 1D: Design for Testability
Abhijit Chatterjee, Georgia Institute of Technology, Atlanta
Yervant Zorian, LogicVision, Inc., San Jose, CA
Rajesh Pendurkar, Georgia Institute of Technology, Atlanta
pp. 69-73
Jih-Jeen Chen, Nat'l Cheng-Kung U., Tainan, Taiwan
Cheng-Hua Huang, Nat'l Cheng-Kung U., Tainan, Taiwan
Kuen-Jong Lee, Nat'l Cheng-Kung U., Tainan, Taiwan
pp. 74-78
Janak H. Patel, University of Illinois, Urbana
Frank F. Hsu, University of Illinois, Urbana
pp. 79-84
Session 2A: Reduced Order Modelling
Janet M. Wang, University of California at Berkeley
Ernest S. Kuh, University of California at Berkeley
Qingjian Yu, University of California at Berkeley
pp. 85-91
Session 2B: Combinational Logic Synthesis
Robert K. Brayton, University of California, Berkeley
Subarnarekha Sinha, University of California, Berkeley
pp. 103-110
Giovanni De Micheli, Stanford University, CA
Shin-ichi Minato, NTT Optical Network Systems Labs., Kanagawa, Japan
pp. 111-117
Session 2C: Topics in Layout
C. L. Liu, National Tsing Hua University, Hsinchu, Taiwan
Prashant Saxena, Intel Corporation, Inc., Hillsboro, OR
pp. 124-127
John P. Hayes, University of Michigan, Ann Arbor
Avaneendra Gupta, Cadence Design Systems, Inc., San Jose, CA
pp. 128-135
Hsiao-Pin Su, Tsing Hua University, Hsin-Chu, Taiwan
Yih-Chih Chou, Tsing Hua University, Hsin-Chu, Taiwan
Youn-Long Lin, Tsing Hua University, Hsin-Chu, Taiwan
Yu-Wen Tsay, Tsing Hua University, Hsin-Chu, Taiwan
Tzu-Chieh Tien, Tsing Hua University, Hsin-Chu, Taiwan
pp. 136-139
Session 2D: Sequential Circuit Testing
Kiran B. Doreswamy, NEC USA Inc., Princeton, NJ
Srimat T. Chakradhar, NEC USA Inc., Princeton, NJ
Surendra K. Bommu, NEC USA Inc., Princeton, NJ
pp. 140-146
W. Kent Fuchs, Purdue University, West Lafayette, IN
Vamsi Boppana, Fujitsu Laboratories of America, Inc., Sunnyvale, CA
pp. 147-154
Session 3A: Numerical Techniques for Simulation and Extraction
M. Zharov, NIISAPRAN, Russian Academy of Sciences, Moscow
S. Rusakov, NIISAPRAN, Russian Academy of Sciences, Moscow
S. Ulyanov, NIISAPRAN, Russian Academy of Sciences, Moscow
M. Gourary, NIISAPRAN, Russian Academy of Sciences, Moscow
K. K. Gullapalli, Motorola Inc., Austin, Texas
B. J. Mulvaney, Motorola Inc., Austin, Texas
pp. 162-169
David E. Long, Lucent Technologies, Murray Hill, NJ
Sharad Kapur, Lucent Technologies, Murray Hill, NJ
pp. 178-185
Session 3B: Intellectual Property Protection
Miodrag Potkonjak, The University of California, Los Angeles
William H. Mangione-Smith, The University of California, Los Angeles
John Lach, The University of California, Los Angeles
pp. 186-189
Miodrag Potkonjak, The University of California, Los Angeles
Gang Qu, The University of California, Los Angeles
pp. 190-193
Jason Cong, The University of California, Los Angeles
Miodrag Potkonjak, The University of California, Los Angeles
Yean-Yow Hwang, The University of California, Los Angeles
Darko Kirovski, The University of California, Los Angeles
pp. 194-198
Session 4A: Embedded Tutorial - Estimating Noise in RF Systems
Alper Demir, Bell Laboratories, Murray Hill, New Jersey
Jaijeet Roychowdhury, Bell Laboratories, Murray Hill, New Jersey
pp. 199-202
Session 4B: Embedded Tutorial - Getting to the Bottom of Deep Submicron
Kurt Keutzer, University of California, Berkeley
Dennis Sylvester, University of California, Berkeley
pp. 203-211
Session 5A: Noise in Digital Systems
Karthik Rajagopal, Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi, Carnegie Mellon University, Pittsburgh, PA
Ravishankar Arunachalam, Carnegie Mellon University, Pittsburgh, PA
Paul D. Gross, Carnegie Mellon University, Pittsburgh, PA
pp. 212-219
Ruud A. Haring, IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Chandu Visweswariah, IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Andrew R. Conn, IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 220-227
Naresh R. Shanbhag, University of Illinois at Urbana-Champaign
Rajamohana Hegde, University of Illinois at Urbana-Champaign
pp. 228-234
Session 5B: Pass Transistor and Domino Logic Synthesis
M. Poncino, Politecnico di Torino, Italy
R. Scarsi, Politecnico di Torino, Italy
A. Macii, Politecnico di Torino, Italy
E. Macii, Politecnico di Torino, Italy
F. Somenzi, University of Colorado, Boulder
F. Ferrandi, Politecnico di Milano, Italy
pp. 235-241
Carl Sechen, University of Washington, Seattle
Gin Yee, University of Washington, Seattle
Tyler Thorp, University of Washington, Seattle
pp. 242-247
Sachin S. Sapatnekar, University of Minnesota, Minneapolis
Min Zhao, University of Minnesota, Minneapolis
pp. 248-251
Session 5C: Floorplanning
D. F. Wong, The University of Texas at Austin
F. Y. Young, The University of Texas at Austin
pp. 252-258
Wayne Wei-Mingi Dai, University of California at Santa Cruz
Maggie Zhiwei Kang, Cadence Design Systems, Inc.
pp. 259-266
Session 5D: Test Generation Techniques
Prem R. Menon, University of Massachusetts, Amherst
Ramesh C. Tekumalla, Intel Corporation, Hillsboro
pp. 275-282
Janak H. Patel, University of Illinois, Urbana
Ilker Hamzaoglu, University of Illinois, Urbana
pp. 283-289
Session 6A: Analog Circuit Synthesis
Stephen P. Boyd, Stanford University, CA
Thomas H. Lee, Stanford University, CA
Maria del Mar Hershenson, Stanford University, CA
pp. 296-303
Willy Sansen, Katholieke Universiteit Leuven, Belgium
Georges Gielen, Katholieke Universiteit Leuven, Belgium
Franky Leyn, Katholieke Universiteit Leuven, Belgium
pp. 304-307
Georges Gielen, Katholieke Universiteit Leuven, Belgium
Geert Debyser, Katholieke Universiteit Leuven, Belgium
pp. 308-311
Session 6B: Timing Optimization in Sequential Synthesis
Maciej Ciesielski, University of Massachusetts, Amherst
Balakrishnan Iyer, University of Massachusetts, Amherst
pp. 312-315
Carl Ebeling, University of Washington, Seattle
Soha Hassoun, Tufts University, Medford, MA
pp. 316-323
Alex Kondratyev, The University of Aizu, Japan
Alex Yakovlev, University of Newcastle upon Tyne, UK
Alexander Taubin, The University of Aizu, Japan
Luciano Lavagno, Politecnico di Torino, Italy
Michael Kishinevsky, Intel Corp., Hillsboro, Oregon
Jordi Cortadella, Univ. Polit?cnica de Catalunya, Barcelona, Spain
pp. 324-331
Session 6C: Issues in High-Level Synthesis
Naresh Sehgal, Intel Corporation, Santa Clara, CA
Phani Saripella, Intel Corporation, Santa Clara, CA
Rajesh Gupta, University of California, Irvine
Sudhakar Kale, Intel Corporation, Santa Clara, CA
Amit Chowdhary, Intel Corporation, Santa Clara, CA
pp. 332-339
Session 6D: Sequential Verification
Jae-Young Jang, University of Colorado, Boulder
Jun Yuan, Motorola Inc., Austin, TX
Carl Pixley, Motorola Inc., Austin, TX
Fabio Somenzi, University of Colorado, Boulder
Gary D. Hachtel, University of Colorado, Boulder
In-Ho Moon, University of Colorado, Boulder
pp. 351-358
Limor Fix, Intel Israel Ltd., Haifa
Gila Kamhi, Intel Israel Ltd., Haifa
pp. 359-365
Session 7A: Analog Test and Layout
Terri Fiez, Washington State University, Pullman
Ravindranath Naiknaware, Washington State University, Pullman
pp. 371-375
Jinyan Zhang, University of Washington
Mani Soma, University of Washington
Seongwon Kim, University of Washington
Sam D. Huynh, University of Washington
pp. 376-383
Abhijit Chatterjee, Georgia Institute of Technology, Atlanta
Junwei Hou, Georgia Institute of Technology, Atlanta
pp. 384-391
Session 7B: Timing Optimization of Sequential Circuits
Katsumasa Watanabe, Nara Institute of Science and Technology, Japan
Kazuyoshi Takagi, Nara Institute of Science and Technology, Japan
Shinji Kimura, Nara Institute of Science and Technology, Japan
Kazuhiro Nakamura, Nara Institute of Science and Technology, Japan
pp. 392-395
Robert K. Brayton, University of California, Berkeley
Vigyan Singhal, Cadence Berkeley Labs, CA
Fabio Somenzi, University of Colorado, Boulder
Rajeev K. Ranjan, Synopsys Inc., Mountain View, CA
pp. 402-407
Session 7C: Partitioning and Floorplanning
TingTing Hwang, National Tsing Hua University, HsinChu, Taiwan
C. L. Liu, National Tsing Hua University, HsinChu, Taiwan
Chau-Shen Chen, National Tsing Hua University, HsinChu, Taiwan
pp. 408-411
Miriam Leeser, Northeastern University, Boston, MA
Zixin Yin, Northeastern University, Boston, MA
Shantanu Tarafdar, Synopsys Inc., Mountain View, CA
pp. 412-417
Keishi Sakanushi, Tokyo Institute of Technology
Masahiro Kawakita, Toshiba Corporation
Yoji Kajitani, Tokyo Institute of Technology
Shigetoshi Nakatake, Tokyo Institute of Technology
pp. 418-425
Session 7D: Memory and Interfaces Synthesis
Youn-Long Lin, Tsing Hua University, Hsin-Chu, Taiwan
Yih-Chih Chou, Tsing Hua University, Hsin-Chu, Taiwan
pp. 426-429
Gaetano Borriello, University of Washington, Seattle
Ross B. Ortega, University of Washington, Bothell
pp. 437-444
Session 8A: Embedded Tutorial - Core-Based Design
Session 8B: Embedded Tutorial - Full-Chip Verification of UDSM Designs
S. Taylor, CMOS Solutions, Olga, WA
D. Overhauser, Simplex Solutions, Sunnyvale, CA
R. Saleh, Simplex Solutions, Sunnyvale, CA
pp. 453-460
Session 9A: Efficient Power Estimation
Luca Benini, DEIS - Universit? di Bologna - Italy
Alessandro Bogliolo, DEIS - Universit? di Bologna - Italy
pp. 461-467
Kaushik Roy, Purdue Univ., W. Lafayette, IN
Edwin K. P. Chong, Purdue Univ., W. Lafayette, IN
Zhanping Chen, Purdue Univ., W. Lafayette, IN
pp. 468-472
C. L. Liu, National Tsing Hua University
Ali Pinar, University of Illinois at Urbana-Champaign
pp. 473-476
Session 9B: Optimization Techniques
Arlindo L. Oliveira, Cadence European Labs/IST-INESC, Lisboa, Portugal
Jorge M. Pena, IST-INESC, Lisboa, Portugal
pp. 482-489
Session 9C: Circuit Partitioning
D. F. Wong, University of Texas at Austin, TX
Huiqun Liu, University of Texas at Austin, TX
pp. 497-504
Sverre Wichlund, Alcatel Telecom Norway
Einar J. Aas, Norwegian University of Science and Technology
pp. 505-511
Sung Kyu Lim, UCLA Department of Computer Science, Los Angeles
Jason Cong, UCLA Department of Computer Science, Los Angeles
pp. 512-516
Session 9D: System-Level Verification
Akira Mukaiyama, C&C Research Labs, NEC USA, Princeton, NJ
Anand Raghunathan, C&C Research Labs, NEC USA, Princeton, NJ
Subhrajit Bhattacharya, C&C Research Labs, NEC USA, Princeton, NJ
Pranav Ashar, C&C Research Labs, NEC USA, Princeton, NJ
pp. 517-524
Lisa M. Guerra, Rockwell Semiconductor Systems, Newport Beach
Miodrag Potkonjak, University of California, Los Angeles
Darko Kirovski, University of California, Los Angeles
pp. 525-528
Session 10A: Delay Modeling and Optimization
Hidetoshi Onodera, Kyoto University, Sakyo-ku, Japan
Keikichi Tamaru, Kyoto University, Sakyo-ku, Japan
Akio Hirata, Kyoto University, Sakyo-ku, Japan
pp. 537-544
Leon Stok, IBM TJ Watson Research Center, Yorktown Heights, NY
Prabhakar Kudva, IBM TJ Watson Research Center, Yorktown Heights, NY
David Kung, IBM TJ Watson Research Center, Yorktown Heights, NY
Frederik Beeftink, Delft University of Technology, The Netherlands
pp. 545-550
M. Pedram, Univ. of Southern California, Los Angeles
M. Zamboni, Politecnico di Torino, Italy
G. Piccinini, Politecnico di Torino, Italy
P. Cocchini, Politecnico di Torino, Italy
pp. 551-556
Session 10B: Combinational and Sequential Equivalence Checking
Anmol Mathur, Ambit Design Systems
Prithviraj Banerjee, Northwestern University
Gagan Hasteer, Ambit Design Systems
pp. 557-562
Vigyan Singhal, Cadence Berkeley Labs
Jerry R. Burch, Cadence Berkeley Labs
pp. 570-576
Session 10C: Scheduling in High-Level Synthesis
Paul C. N. van Gorp, Endhoven University of Technology, The Netherlands
Emile H. L. Aarts, Philips Research Laboratories, The Netherlands; Endhoven University of Technology, The Netherlands
Wim F. J. Verhaegh, Philips Research Laboratories, The Netherlands
pp. 585-592
J. Ramanujam, Louisiana State University, Baton Rouge
M. Narasimhan, Louisiana State University, Baton Rouge
pp. 593-596
Session 10D: Issues in Power Analysis and Optimization
Miodrag Potkonjak, University of California, Los Angeles
Gang Qu, University of California, Los Angeles
pp. 597-600
Harm Arts, Ambit Design Systems, Santa Clara, CA
Prithviraj Banerjee, Northwestern University, Evanston, IL
Sumit Roy, Ambit Design Systems, Santa Clara, CA
pp. 601-606
S. Nikolaidis, University of Thessaloniki, Greece
A. Tatsaki, Silicon Graphics, Mountain View, CA
E. D. Kyriakis-Bitzaros, NCSR "Demokritos", Greece
pp. 607-610
Session 11A: Advances in Interconnect Optimization
Chris C. N. Chu, University of Texas at Austin, TX
D. F. Wong, University of Texas at Austin, TX
Chung-Ping Chen, University of Texas at Austin, TX
pp. 617-624
Jinan Lou, University of Southern California, Los Angeles
Massoud Pedram, University of Southern California, Los Angeles
Amir H. Salek, University of Southern California, Los Angeles
pp. 625-630
Session 11B: Improved and Characterizing BDD Performance
Masahiro Fujita, Fujitsu Labs of America, Sunnyvale, CA
William Adams, University of Texas, Austin
Jawahar Jain, Fujitsu Labs of America, Sunnyvale, CA
pp. 631-638
Session 11C: System Synthesis Under Design Constraints
Mani B. Srivastava, University of California, Los Angeles
Miodrag Potkonjak, University of California, Los Angeles
Inki Hong, University of California, Los Angeles
pp. 653-656
Anand Raghunathan, CCRL, NEC-USA, Princeton, NJ
Niraj K. Jha, Princeton University, NJ
Sujit Dey, University of California, San Diego
Ganesh Lakshminarayana, Princeton University, NJ
pp. 657-664
In-Cheol Park, Korea Advanced Institute of Sciencea and Technology, Taejon, Korea
Seung Ho Hwang, Korea Advanced Institute of Sciencea and Technology, Taejon, Korea
Chong-Min Kyung, Korea Advanced Institute of Sciencea and Technology, Taejon, Korea
Hoon Choi, Korea Advanced Institute of Sciencea and Technology, Taejon, Korea
pp. 665-671
Session 11D: Functional Representation
Thomas M. Weis, Albert-Ludwigs-University, Germany
Bernd Becker, Albert-Ludwigs-University, Germany
Christoph Scholl, Albert-Ludwigs-University, Germany
pp. 672-677
Giovanni De Micheli, Stanford University, CA
James Smith, Stanford University, CA
pp. 678-685
Lothar Thiele, Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
Karsten Strehl, Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
pp. 686-692
Session 12A: Embedded Tutorial - Interface Synthesis: A Vertical Slice from Digital Logic to Software Components
Luciano Lavagno, Politecnico di Torino, Italia
Ross B. Ortega, University of Washington, Bothell
Gaetano Borriello, University of Washington, Seattle
pp. 693-695
Session 12B: Embedded Tutorial - Dynamic Power Management of Electronic Systems
Alessandro Bogliolo, DEIS - Universit? di Bologna
Giovanni De Micheli, CSL - Stanford University
Luca Benini, DEIS - Universit? di Bologna
pp. 696-702
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