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1997 International Conference on Computer-Aided Design (ICCAD '97)
San Jose, CA
November 09-November 13
ISBN: 0-8186-8200-0
Table of Contents
Session 1A: Decision Diagram Applications, Moderators: Shin-ichi Minato and Jawahar Jain
Christoph Scholl, Albert-Ludwigs-University
Rolf Drechsler, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
pp. 8
P. Vuillod, Comput. Syst. Lab., Stanford Univ., CA, USA
L. Benini, Comput. Syst. Lab., Stanford Univ., CA, USA
G. De Micheli, Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 13
Session 1B: Optimization and Synthesis for Reactive Systems, Moderators: Rolf Ernst and Charles Rosenthal
Jian Li, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
R.K. Gupta, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 22
Chi-Hong Hwang, Dept. of Comput. Sci., Tsinghua Univ., Beijing, China
A.C.-H. Wu, Dept. of Comput. Sci., Tsinghua Univ., Beijing, China
pp. 28
Kyosun Kim, University of Massachusetts
Ramesh Karri, University of Massachusetts
Miodrag Potkonjak, University of California, Los Angeles
pp. 33
Session 1C: Estimation of Power Bounds, Moderators: Farid N. Najm and Wen-Zen Shen
Zhanping Chen, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
Tan-Li Chou, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 40
Chuan-Yu Wang, Electrical and Computer Engineering Purdue University, West Lafayette
Kaushik Roy, Electrical and Computer Engineering Purdue University, West Lafayette
pp. 52
Session 1D: Block Krylov Methods for Interconnect Modeling, Moderators: Peter Feldmann and Jacob K. White
A. Odabasioglu, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
M. Celik, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 58
Session 2A: Multi-Level Synthesis and Covering Problem, Moderators: Robert J. Francis and Olivier Courdert
Rajat Aggarwal, Lattice Semiconductor Corporation, Milpitas, CA
Rajeev Murgai, Fujitsu Labs of America, Inc.
Masahiro Fujita, Fujitsu Labs of America, Inc.
pp. 83
Evguenii I. Goldberg, University of California at Berkeley, CA 94720.
Luca P. Carloni, University of California at Berkeley, CA 94720.
Robert K. Brayton, University of California at Berkeley, CA 94720.
Alberto L. Sangiovanni-Vincentelli, University of California at Berkeley, CA 94720.
Tiziano Villa, PARADES
pp. 91
Session 2B: Code Generation and Processor Design, Moderators: P.A. Subrahmanyam and Rolf Ernst
Darko Kirovski, University of California, Los Angeles
Chunho Lee, University of California, Los Angeles
Miodrag Potkonjak, University of California, Los Angeles
William Mangione-Smith, University of California, Los Angeles
pp. 104
I. Hong, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA.
M. Potonjak, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA.
R. Karri, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA.
pp. 108
Session 2C: High-Level Power Prediction and Reduction, Moderators: Chandu Visweswariah and Wen-Zen Shen
Mahadevamurty Nemani, University of Illinois at Urbana-Champaign
Farid N. Najm, University of Illinois at Urbana-Champaign
pp. 114
Sumant Ramprasad, Coordinated Science Laboratory University of Illinois at Urbana Champaign
Naresh R. Shanbhag, Coordinated Science Laboratory University of Illinois at Urbana Champaign
Ibrahim N. Hajj, Coordinated Science Laboratory University of Illinois at Urbana Champaign
pp. 126
Session 2D: Noise Analysis and Modeling, Moderators: Lawrence T. Pileggi and Jue Hsien Chern
K. L. Shepard, IBM T. J. Watson Research Center
V. Narayanan, IBM T. J. Watson Research Center
P. C. Elmendorf, IBM Microelectronics, Fishkill, NY
Gutuan Zheng, IBM Microelectronics, Fishkill, NY
pp. 139
Session 3A: High Level Validation, Moderators: Christos Papachristou and Joachim Kunkel
Jeremy Levitt, Computer Systems Laboratory, Stanford University
Kunle Olukotun, Computer Systems Laboratory, Stanford University
pp. 162
Darko Kirovski, University of California, Los Angeles
Miodrag Potkonjak, University of California, Los Angeles
pp. 170
Session 3B: Timing Analysis, Moderators: Chandu Visweswariah and Wen-Zen Shen
Yuji Kukimoto, University of California, Berkeley
Wilsin Gosti, University of California, Berkeley
Robert K. Brayton, University of California, Berkeley
Alexander Saldanha, Cadence Berkeley Laboratories
pp. 176
Session 4A: Embedded Tutorial
4A.1: Microelectromechanical Systems
Session 4B: Embedded Tutorial
Session 5A: Sequential Circuit Optimization, Moderators: Marios Papaefthymiou and Narendra V. Shenoy
Amit Mehrotra, University of California at Berkeley
Shaz Qadeer, University of California at Berkeley
Robert K Brayton, University of California at Berkeley
Alberto L. Sangiovanni-Vincentelli, University of California at Berkeley
Vigyan Singhal, Cadence Berkeley Labs
Adnan Aziz, University of Texas at Austin
pp. 208
J. Cortadella, Univ. Politecnica de Catalunya, Barcelona, Spain
M. Kishinevsky, Univ. Politecnica de Catalunya, Barcelona, Spain
A. Kondratyev, Univ. Politecnica de Catalunya, Barcelona, Spain
L. Lavagno, Univ. Politecnica de Catalunya, Barcelona, Spain
E. Pastor, Univ. Politecnica de Catalunya, Barcelona, Spain
A. Yakovlev, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 220
Session 5B: Advanced Scheduling Techniques, Moderators: Miodrag M. Potkonjak and David Ku
C. Monahan, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
F. Brewer, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 230
Chih-Tung Chen, Unified Design System Laboratory, Motorola, Inc.
Kayhan Kucukcakar, Unified Design System Laboratory, Motorola, Inc.
pp. 236
Session 5C: Clock Design and Optimization, Moderators: Masato Edahiro and Jason Cong
Session 5D: Circuit Simulation and Optimization, Moderators: Ibrahim M. Elfadel and Wim van Bokhoven
Andrew R. Conn, IBM T. J. Watson Research Center
Ruud A. Haring, IBM T. J. Watson Research Center
Chandu Visweswariah, IBM T. J. Watson Research Center
Chai Wah Wu, IBM T. J. Watson Research Center
pp. 281
T.V. Nguyen, Res. Lab., IBM Corp., Austin, TX, USA
A. Devgan, Res. Lab., IBM Corp., Austin, TX, USA
pp. 289
Session 6A: New Ideas in Encoding, Moderators: Ellen M. Sentovich and Pranav Ashar
Evguenii I. Goldberg, Academy of Sciences of Belarus, Minsk
Tiziano Villa, PARADES
Robert K. Brayton, University of California at Berkeley
Alberto L. Sangiovanni-Vincentelli, University of California at Berkeley
pp. 296
Session 6B: Synthesis with Complex Components, Moderators: Forrest D. Brewer and Kunle Olukotun
S. Raje, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R.A. Bergamaschi, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 326
Preeti Ranjan Panda, University of California, Irvine
Nikil D. Dutt, University of California, Irvine
Alexandru Nicolau, University of California, Irvine
pp. 333
Session 6C: Partitioning Part I, Moderators: Naveed Sherwani or Chung-Kuan Cheng
Morgan Enos, Northwestern University
Scott Hauck, Northwestern University
Majid Sarrafzadeh, Northwestern University
pp. 342
Wray L. Buntine, Univ. of California, Berkeley
Lixin Su, Univ. of California, Berkeley
A. Richard Newton, Univ. of California, Berkeley
Andrew Mayer, Univ. of California, Berkeley
pp. 356
Session 6D: Analog Modeling and Testing, Moderators: Wim van Bokhoven and Georges Gielen
Francky Leyn, Katholieke Universiteit Leuven, ESAT-MICAS
Walter Daems, Katholieke Universiteit Leuven, ESAT-MICAS
Georges Gielen, Katholieke Universiteit Leuven, ESAT-MICAS
Willy Sansen, Katholieke Universiteit Leuven, ESAT-MICAS
pp. 374
Session 7A: Sequential Circuit Verification, Chair: Carl P. Pixley and Gianpiero Cabodi
Amit Narayan, University of California, Berkeley
Adrian J. Isles, University of California, Berkeley
Robert K. Brayton, University of California, Berkeley
A. L. Sangiovanni-Vincentelli, University of California, Berkeley
Jawahar Jain, Fujitsu Labs of America
pp. 388
D. Stoffel, Inst. of Comput. Sci. III, Potsdam Univ., Germany
W. Kunz, Inst. of Comput. Sci. III, Potsdam Univ., Germany
pp. 394
Session 7B: BIST, Moderators: Janusz Rajski, or Ronald D. Blanton
C. Papachristou, Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
M. Baklashov, Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 414
Irith Pomeranz, Electrical and Computer Engineering Department, University of Iowa
Sudhakar M. Reddy, Electrical and Computer Engineering Department, University of Iowa
pp. 421
Session 7C: Partitioning Part II, Moderators: Charles J. Alpert and Atsushi Takahashi
Vi Chi Chan, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
D. Lewis, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 428
Jason Y. Zien, IBM Almaden Research Center, San Jose
Pak K. Chan, University of California, Santa Cruz
Martine Schlag, University of California, Santa Cruz
pp. 436
Session 7D: Efficient Techniques for Parasitics Extraction, Moderators: David D. Ling and Sani R. Nassif
S. Kapur, Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
D.E. Long, Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
pp. 448
Mattan Kamon, Massachusetts Institute of Technology
Jacob White, Massachusetts Institute of Technology
Nuno Marques, INESC/Cadence European Labs.
pp. 456
Session 8A: Embedded Tutorial
Session 8B: Embedded Tutorial: Interconnect Design for Deep Submicron ICs
Session 9A: Power Estimation and Modeling, Moderators: Kaushik Roy and Chandu Visweswariah
Joseph N. Kozhaya, University of Illinois at Urbana-Champaign
Farid N. Najm, University of Illinois at Urbana-Champaign
pp. 488
L. Benini, Comput. Syst. Lab., Stanford Univ., CA, USA
G. De Micheli, Comput. Syst. Lab., Stanford Univ., CA, USA
E. Macii, Comput. Syst. Lab., Stanford Univ., CA, USA
M. Poncino, Comput. Syst. Lab., Stanford Univ., CA, USA
R. Scarsi, Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 494
Session 9B: Partitioning for HW/SW Codesign, Moderators: Allen C.-H. Wu and Frank N. Vahid
Session 9C: Placement, Moderators: Dwight D. Hill and Malgorzata Marek-Sadowska
Session 9D: Fault Simulation and Diagnosis, Moderator: Robert Aitken and Kwang-Ting Cheng
Tzuhao Chen, Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
I.N. Hajj, Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 555
Session 10A: Logic Synthesis for Low Power, Moderators: Jordi Cortadella and Luciano Lavagno
Unni Narayanan, University of Illinois at Urbana-Champaign
C. L. Liu, University of Illinois at Urbana-Champaign
pp. 570
Luca P. Carloni, University of California at Berkeley
Alberto L. Sangiovanni-Vincentelli, University of California at Berkeley
Patrick C. McGeer, Cadence Berkeley Laboratories
Alexander Saldanha, Cadence Berkeley Laboratories
pp. 581
Session 10B: Analysis of Real Time Systems, Moderators: Wayne Wolf and Ahmed A. Jerraya
S. Dey, C&C Res. Labs., NEC USA Inc., Princeton, NJ, USA
S. Bommu, C&C Res. Labs., NEC USA Inc., Princeton, NJ, USA
pp. 590
Session 10C: Interconnect Optimization, Moderators: Wayne W.-M. Dai and John M. Cohn
J. Cong, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Lei He, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Cheng-Kok Koh, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Zhigang Pan, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 628
Session 10D: Implication and Test Generation Techniques, Moderators: Pranav Ashar and Jawahar Jain
Keerthi Heragu, University of Illinois at Urbana-Champaign
Janak Patel, University of Illinois at Urbana-Champaign
Vishwani D. Agrawal, AT&T Bell Laboratories
pp. 642
P. Tafertshofer, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
A. Ganz, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
M. Henftling, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 648
Session 11A: Technology Driven Synthesis, Moderators: K.-C. Chen and Shih-Chieh Chang
S. Gavrilov, Res. Inst., Acad. of Sci., Moscow, Russia
A. Glebov, Res. Inst., Acad. of Sci., Moscow, Russia
S. Pullela, Res. Inst., Acad. of Sci., Moscow, Russia
S.C. Moore, Res. Inst., Acad. of Sci., Moscow, Russia
A. Dharchoudhury, Res. Inst., Acad. of Sci., Moscow, Russia
R. Panda, Res. Inst., Acad. of Sci., Moscow, Russia
G. Vijayan, Res. Inst., Acad. of Sci., Moscow, Russia
D.T. Blaauw, Res. Inst., Acad. of Sci., Moscow, Russia
pp. 658
Premal Buch, University of California, Berkeley
Amit Narayan, University of California, Berkeley
A. Richard Newton, University of California, Berkeley
Alberto Sangiovanni-Vincentelli, University of California, Berkeley
pp. 663
Jinan Lou, University of Southern California, Los Angeles
Amir H. Salek, University of Southern California, Los Angeles
Massoud Pedram, University of Southern California, Los Angeles
pp. 671
Session 11B: System Specification and Product Engineering, Moderators: Bernard Courtois and Jerry R. Burch
Sang-Hoon Lee, CAE, Semiconductor R & D Center, Samsung Electronics Co., LTD.
Chang-Hoon Choi, CAE, Semiconductor R & D Center, Samsung Electronics Co., LTD.
Jeong-Taek Kong, CAE, Semiconductor R & D Center, Samsung Electronics Co., LTD.
Won-Seong Lee, CAE, Semiconductor R & D Center, Samsung Electronics Co., LTD.
Jei-Hwan Yoo, CAE, Semiconductor R & D Center, Samsung Electronics Co., LTD.
pp. 678
Session 11C: Performance-Driven Routing, Moderators: D.F. Wong and Rajeev Jayaraman
Maggie Kang, University of California at Santa Cruz, CA, 95064
Wayne W.-M. Dai, University of California at Santa Cruz, CA, 95064
Tom Dillinger, Rockwell Semiconductor
David LaPotin, IBM Austin Research Lab
pp. 707
J. Cong, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Cheng-Kok Koh, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 713
Session 11D: Test Theory and Applications, Moderators: Fadi Maamari and Sandeep K. Gupta
Sying-Jyan Wang, National Chung-Hsing University
Tsi-Ming Tsai, National Chung-Hsing University
pp. 722
Michael Kishinevsky, The University of Aizu
Alexander Taubin, The University of Aizu
Alex Kondratyev, The University of Aizu
Luciano Lavagno, Politecnico di Torino
Alexander Saldanha, Cadence Berkeley Laboratories
pp. 728
D. Kagaris, Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
S. Tragoudas, Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 736
Session 12A: Embedded Tutorial
Session 12B: Embedded Tutorial
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