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1996 International Conference on Computer-Aided Design (ICCAD '96)
San Jose, CA
November 10-November 14
ISBN: 0-8186-7597-7
Table of Contents
Session 1A: Technology Mapping, Moderators: Sujit Dey, Bob Francis
R. Puri, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
A. Bjorksten, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
T.E. Rosser, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 2
Juinn-Dar Huang, National Chiao Tung University
Jing-Yang Jou, National Chiao Tung University
Wen-Zen Shen, National Chiao Tung University
pp. 13
Session 1B: Interconnect Characterization and Analysis, Moderators: John Cohn, Chandu Visweswariah
Guowu Zheng, Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Qi-Jun Zhang, Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
M. Nakhla, Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
R. Achar, Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
pp. 20
S.D. Corey, Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
A.T. Yang, Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 24
A.B. Kahng, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
K. Masuko, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
S. Muddu, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 30
Session 1C: High Performance Routing Synthesis, Moderators: Chung Kuan Cheng, Ren-Song Tsay
Chung-Ping Chen, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Hai Zhou, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 38
Session 1D: Sequential Circuit Testing, Moderators: Janusz Rajski or Sandeep Gupta
Wanlin Cao, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D.K. Pradhan, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 56
I. Hartanto, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
V. Boppana, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 63
Session 2A: Formal Verification I, Moderators: Jerry Burch, Felice Balarin
Woohyuk Lee, ECEN Campus, Colorado Univ., Boulder, CO, USA
A. Pardo, ECEN Campus, Colorado Univ., Boulder, CO, USA
Jae-Young Jang, ECEN Campus, Colorado Univ., Boulder, CO, USA
G. Hachtel, ECEN Campus, Colorado Univ., Boulder, CO, USA
F. Somenzi, ECEN Campus, Colorado Univ., Boulder, CO, USA
pp. 76
Hiroaki Iwashita, Fujitsu Laboratories Ltd.
Tsuneo Nakata, Fujitsu Laboratories Ltd.
Fumiyasu Hirose, Fujitsu Laboratories Ltd.
pp. 82
D.K. Pradhan, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D. Paul, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
M. Chatterjee, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 88
Session 2B: System Design: Synthesis and Compilation, Moderators: Rajesh K. Gupta, Hiroto Yasuura
Wei Zhao, Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
C.A. Papachristou, Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 103
Session 2C: Timing Analysis, Moderators: Marios Papaefthymiou, Thomas G. Szymanski
Hakan Yalcin, The University of Michigan
John P. Hayes, The University of Michigan
Karem A. Sakallah, The University of Michigan
pp. 114
Vinod Narayanan, IBM T.J Watson Research Center
Bruce M. Fleischer, IBM T.J Watson Research Center
Barbara A. Chappell, Intel Corporation
pp. 119
D. Van Campenhout, EECS Dept., Michigan Univ., Ann Arbor, MI, USA
T. Mudge, EECS Dept., Michigan Univ., Ann Arbor, MI, USA
K.A. Sakallah, EECS Dept., Michigan Univ., Ann Arbor, MI, USA
pp. 127
Session 2D: Support for High Level Design, Moderator: Michaela Guiney
Eric W. Johnson, University of Notre Dame
Jay B. Brockman, University of Notre Dame
Rik Vigeland, Mentor Graphics Corporation
pp. 142
Session 3A: Power and Performance in High Level Synthesis, Moderators: Forrest Brewer, Wolfgang Rosenstiel
A. Raghunathan, Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Dey, Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha, Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 158
Session 3B: High-Performance Circuit Optimization, Moderators: Willem van Bokhoven, Georges Gielen
Andrew R. Conn, IBM T. J. Watson Research Center
Ruud A. Haring, IBM T. J. Watson Research Center
Chandu Visweswariah, IBM T. J. Watson Research Center
Paula K. Coulman, IBM Microelectronics Division
Gregory L. Morrill, IBM Microelectronics Division
pp. 174
Jason Cong, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Lei He, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 181
Edoardo Charbon, Cadence Design Systems Inc.
Enrico Malavasi, Cadence Design Systems Inc.
Paolo Miliozzi, University of California, Berkeley
Alberto Sangiovanni-Vincentelli, University of California, Berkeley
pp. 187
Session 3C: Circuit Partitioning, Moderators: Jason Kong, Rajeev Jayaraman
Shantanu Dutt, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Wenyong Deng, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 194
Jason Y. Zien, University of California at Santa Cruz
Martine D. F. Schlag, University of California at Santa Cruz
Pak K. Chan, University of California at Santa Cruz
pp. 201
Wai-Kei Mak, University of Texas at Austin
D. F. Wong, University of Texas at Austin
pp. 205
Session 3D: ATPG, Moderators: Wolfgang Kunz, Dhiraj K. Pradhan
Alok Agrawal, University of California Berkeley
Alberto L. Sangiovanni-Vincentelli, University of California Berkeley
Alexander Saldanha, Cadence Berkeley Laboratories
Luciano Lavagno, Cadence Berkeley Laboratories
pp. 212
Session 4A: Embedded Tutorial, Presenter: Edward A. Lee
E.A. Lee, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 234
Session 4B: Embedded Tutorial, Presenters: Nick P. van der Meijs, Theo Smedes
Session 5A: Implication-Based Logic Synthesis, Moderators: Michel Berkelaar, Albert Wang
Shigeru Yamashita, NTT Communication Science Laboratories
Hiroshi Sawada, NTT Communication Science Laboratories
Akira Nagoya, NTT Communication Science Laboratories
pp. 254
Shih-Chieh Chang, Nat. Chung-Cheng Univ., Jay-Yi, Taiwan
L.P.P.P. van Ginneken, Nat. Chung-Cheng Univ., Jay-Yi, Taiwan
M. Marek-Sadowska, Nat. Chung-Cheng Univ., Jay-Yi, Taiwan
pp. 262
Session 5B: Advanced Numerical Simulation Techniques, Moderators: Chandu Visweswariah, Willem van Bokhoven
L. Miguel Silveira, IST/INESC
Mattan Kamon, Massachusetts Institute of Technology
Jacob White, Massachusetts Institute of Technology
Ibrahim Elfadel, IBM T. J. Watson Research Center
pp. 288
Session 5C: Robust RoutingGary Yaep, Takashi Kambe
J.G. Xi, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
W.W.-M. Dai, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 316
Session 5D: BIST and DFT, Moderators: Yervant Zorian, Robert C. Aitken
Bit-Flipping BIST (Abstract)
Hans-Joachim Wunderlich, University of Stuttgart, Germany
Gundolf Kiefer, University of Stuttgart, Germany
pp. 337
Session 6A: Formal Verification II, Moderators: Fabio Somenzi, Ellen M. Sentovich
Yirng-An Chen, Carnegie Mellon University
Randal E. Bryant, Carnegie Mellon University
pp. 361
Session 6B: Yield and Technology Modeling, Moderators: Jacob K. White, David Ling
Eric Felt, University of California, Berkeley
Alberto Sangiovanni-Vincentelli, University of California, Berkeley
Stefano Zanella, Universita degli Studi di Padova
Carlo Guardiani, SGS-Thomson Microelectronics
pp. 374
W. Hong, Dept. of Radio Eng., Southeast Univ., Nanjing, China
W. Sun, Dept. of Radio Eng., Southeast Univ., Nanjing, China
Z. Zhu, Dept. of Radio Eng., Southeast Univ., Nanjing, China
H. Ji, Dept. of Radio Eng., Southeast Univ., Nanjing, China
B. Song, Dept. of Radio Eng., Southeast Univ., Nanjing, China
W. Wei-Ming Dai, Dept. of Radio Eng., Southeast Univ., Nanjing, China
pp. 381
Session 6C: Topics in Power and Timing Analysis, Moderators: Thomas G. Szymanski, Murray Hill
Ashok Vittal, Silicon Graphics Inc.
Hien Ha, University of California, Santa Barbara
Forrest Brewer, University of California, Santa Barbara
Malgorzata Marek-Sadowska, University of California, Santa Barbara
pp. 395
Session 6D: Verification and Fault Tolerance, Moderators: Kunle Olukotun, Steve Tjiang
Session 7A: Extending the Scope of High-Level Synthesis, Moderators: Don MacMillen, Yuon-Long Lin
Ellen M. Sentovich, Ecole Nationale Superieure des Mines de Paris
Horia Toma, Ecole Nationale Superieure des Mines de Paris
Gerard Berry, Ecole Nationale Superieure des Mines de Paris
pp. 428
Ki-Seok Chung, University of Illinois at Urbana-Champaign
Rajesh K. Gupta, University of Illinois at Urbana-Champaign
C.L. Liu, University of Illinois at Urbana-Champaign
pp. 442
Session 7B: Analog CAD and Methodology, Moderators: Georges Gielen, John Cohn
Chad Young, Georgia Institute of Technology
Jonathan Fowler, Georgia Institute of Technology
Paul Kerstetter, Georgia Institute of Technology
Giorgio Casinovi, Georgia Tech Research Institute
pp. 450
Edoardo Charbon, Cadence Design Systems Inc.
Ranjit Gharpurey, Texas Instruments Inc.
Robert G. Meyer, University of California, Berkeley, CA
Alberto Sangiovanni-Vincentelli, University of California, Berkeley, CA
pp. 455
Iasson Vassiliou, University of California, Berkeley
Alper Demir, University of California, Berkeley
Paolo Miliozzi, University of California, Berkeley
Alberto Sangiovanni-Vincentelli, University of California, Berkeley
Henry Chang, Cadence Design Systems, Inc.
Edoardo Charbon, Cadence Design Systems, Inc.
pp. 463
Session 7C: Partitioning and Floorplan, Moderators: Martin D.F. Wong, Frank M. Johannes
Dirk Behrens, University of Hanover
Klaus Harbich, University of Hanover
Erich Barke, University of Hanover
pp. 470
Shigetoshi Nakatake, Tokyo Institute of Technology
Yoji Kajitani, Tokyo Institute of Technology
Kunihiro Fugiyoshi, Japan Advanced Institute of Science and Technology (JAIST)
Hiroshi Murata, Japan Advanced Institute of Science and Technology (JAIST)
pp. 484
Session 7D: Delay Fault Test, Moderators: E.J. McCluskey, Ray Mercer
Keerthi Heragu, University of Illinois at Urbana-Champaign
Janak H. Patel, University of Illinois at Urbana-Champaign
pp. 502
Session 8A: Embedded Tutorial, Presenter: Gordon W. Roberts
G.W. Roberts, Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
pp. 514
Session 8B: Embedded Tutorial, Presenters: Ken L. Shepard, Vinod Narayanan
Kenneth L. Shepard, IBM T. J. Watson Research Center
Vinod Narayanan, IBM T. J. Watson Research Center
pp. 524
Session 9A: Panel
Session 10A: BDD Applications and Techniques, Moderators: Albert Wang, Sujit Dey
Scott Woods, Georgia Institute of Technology
Giorgio Casinovi, Georgia Tech Research Institute
pp. 542
A. Narayan, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
J. Jain, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
M. Fujita, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 547
Session 10B: Advances in Transmission Line Analysis, Moderators: Chandu Visweswariah, Rob A. Rutenbar
Jun-Fa Mao, University of California at Berkeley
Janet Meiling Wang, University of California at Berkeley
Ernest S. Kuh, University of California at Berkeley
pp. 556
Session 1OC: Power and Current Modeling, Moderators: Farid N. Najm, Jyuo-Min Shyu
Cheng-Ta Hsieh, Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Qing Wu, Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Chih-Shun Ding, Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram, Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 583
Session 10D: Mixed-Signal Testing, Moderators: Ranga Vemuri, Gordon Roberts
Chanchin Su, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Yue-Tsang Chen, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Shyh-Jye Jou, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Yuan-Tzu Ting, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 594
Session 11A: Logic Synthesis, Moderators: Narendra Shenoy, Carl Pixley
Balakrishnan Iyer, University of Massachusetts at Amherst
Maciej Ciesielski, University of Massachusetts at Amherst
pp. 614
Vigyan Singhal, Cadence Berkeley Labs
Sharad Malik, Princeton University
Robert K. Brayton, University of California at Berkeley
pp. 618
Session 11B: System Level Optimization and Validation, Moderators: P.A. Subrahmanyam, Masaharu Imai
I. Hong, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Potkonjak, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 634
Session 11C: Special Topics In Physical Design, Moderators: Dwight Hill, Atushi Takahashi
Man-Fai Yu, Board of Studies in Comput. Eng., California Univ., Santa Cruz, CA, USA
J. Darnauer, Board of Studies in Comput. Eng., California Univ., Santa Cruz, CA, USA
W.W.-M. Dai, Board of Studies in Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 668
Session 11D: Fault Diagnosis, Moderators: Rabindra K. Roy, Justin Harlow
V. Boppana, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 681
K. Chakraborty, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
P. Mazumder, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 685
Session 12A: Embedded Tutorial, Presenters: W. Maly, H. Heineken, J. Khare, P.K. Nag
W. Maly, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
H. Heineken, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J. Khare, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
P.K. Nag, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 690
Session 12B: Embedded Tutorial, Presenter: L.P.P.P. van Ginneken, N.V. Shenoy, R.H.J.M. Otten
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