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Computer-Aided Design, International Conference on (1996)
San Jose, CA
Nov. 10, 1996 to Nov. 14, 1996
ISBN: 0-8186-7597-7
TABLE OF CONTENTS
Session 1A: Technology Mapping, Moderators: Sujit Dey, Bob Francis
A. Bjorksten , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R. Puri , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 2
Jing-Yang Jou , National Chiao Tung University
Juinn-Dar Huang , National Chiao Tung University
pp. 13
Session 1B: Interconnect Characterization and Analysis, Moderators: John Cohn, Chandu Visweswariah
Qi-Jun Zhang , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
M. Nakhla , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
R. Achar , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
pp. 20
S.D. Corey , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
A.T. Yang , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 24
A.B. Kahng , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
K. Masuko , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
S. Muddu , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 30
Session 1C: High Performance Routing Synthesis, Moderators: Chung Kuan Cheng, Ren-Song Tsay
Chung-Ping Chen , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 38
Daksh Lehther , Iowa State University
pp. 50
Session 1D: Sequential Circuit Testing, Moderators: Janusz Rajski or Sandeep Gupta
Wanlin Cao , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 56
I. Hartanto , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
V. Boppana , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 63
Elizabeth M. Rudnick , University of Illinois
Janak H. Patel , University of Illinois
pp. 67
Session 2A: Formal Verification I, Moderators: Jerry Burch, Felice Balarin
A. Pardo , ECEN Campus, Colorado Univ., Boulder, CO, USA
Jae-Young Jang , ECEN Campus, Colorado Univ., Boulder, CO, USA
G. Hachtel , ECEN Campus, Colorado Univ., Boulder, CO, USA
F. Somenzi , ECEN Campus, Colorado Univ., Boulder, CO, USA
pp. 76
Hiroaki Iwashita , Fujitsu Laboratories Ltd.
Fumiyasu Hirose , Fujitsu Laboratories Ltd.
pp. 82
D. Paul , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
M. Chatterjee , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 88
Session 2B: System Design: Synthesis and Compilation, Moderators: Rajesh K. Gupta, Hiroto Yasuura
Wei Zhao , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 103
Rainer Leupers , University of Dortmund
Peter Marwedel , University of Dortmund
pp. 109
Session 2C: Timing Analysis, Moderators: Marios Papaefthymiou, Thomas G. Szymanski
John P. Hayes , The University of Michigan
Hakan Yalcin , The University of Michigan
pp. 114
Bruce M. Fleischer , IBM T.J Watson Research Center
Vinod Narayanan , IBM T.J Watson Research Center
pp. 119
T. Mudge , EECS Dept., Michigan Univ., Ann Arbor, MI, USA
D. Van Campenhout , EECS Dept., Michigan Univ., Ann Arbor, MI, USA
pp. 127
Session 2D: Support for High Level Design, Moderator: Michaela Guiney
Gunther Lehmann , University of Karlsruhe
Klaus D. Mueller-Glaser , University of Karlsruhe
pp. 134
Jay B. Brockman , University of Notre Dame
Eric W. Johnson , University of Notre Dame
pp. 142
Session 3A: Power and Performance in High Level Synthesis, Moderators: Forrest Brewer, Wolfgang Rosenstiel
S. Dey , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 158
Session 3B: High-Performance Circuit Optimization, Moderators: Willem van Bokhoven, Georges Gielen
Ruud A. Haring , IBM T. J. Watson Research Center
Chandu Visweswariah , IBM T. J. Watson Research Center
Paula K. Coulman , IBM Microelectronics Division
Gregory L. Morrill , IBM Microelectronics Division
pp. 174
Jason Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 181
Edoardo Charbon , Cadence Design Systems Inc.
Enrico Malavasi , Cadence Design Systems Inc.
Paolo Miliozzi , University of California, Berkeley
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
pp. 187
Session 3C: Circuit Partitioning, Moderators: Jason Kong, Rajeev Jayaraman
Shantanu Dutt , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 194
Martine D. F. Schlag , University of California at Santa Cruz
Pak K. Chan , University of California at Santa Cruz
pp. 201
Wai-Kei Mak , University of Texas at Austin
pp. 205
Session 3D: ATPG, Moderators: Wolfgang Kunz, Dhiraj K. Pradhan
Alok Agrawal , University of California Berkeley
Alberto L. Sangiovanni-Vincentelli , University of California Berkeley
Alexander Saldanha , Cadence Berkeley Laboratories
Luciano Lavagno , Cadence Berkeley Laboratories
pp. 212
Karem A. Sakallah , University of Michigan
pp. 220
Session 4A: Embedded Tutorial, Presenter: Edward A. Lee
E.A. Lee , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 234
Session 4B: Embedded Tutorial, Presenters: Nick P. van der Meijs, Theo Smedes
N.P. Van der Meijs , Delft University of Technology
T. Smedes , Philips Semiconductors
pp. 244
Session 5A: Implication-Based Logic Synthesis, Moderators: Michel Berkelaar, Albert Wang
Hiroshi Sawada , NTT Communication Science Laboratories
Shigeru Yamashita , NTT Communication Science Laboratories
pp. 254
Shih-Chieh Chang , Nat. Chung-Cheng Univ., Jay-Yi, Taiwan
L.P.P.P. van Ginneken , Nat. Chung-Cheng Univ., Jay-Yi, Taiwan
M. Marek-Sadowska , Nat. Chung-Cheng Univ., Jay-Yi, Taiwan
pp. 262
Qi Wang , University of Arizona
Sarma B. K. Vrudhula , University of Arizona
pp. 270
Session 5B: Advanced Numerical Simulation Techniques, Moderators: Chandu Visweswariah, Willem van Bokhoven
Mattan Kamon , Massachusetts Institute of Technology
Jacob White , Massachusetts Institute of Technology
L. Miguel Silveira , IST/INESC
pp. 288
Session 5C: Robust RoutingGary Yaep, Takashi Kambe
Ernest S. Kuh. , Univ. of CA at Berkeley
Tianxiong Xue , Univ. of CA at Berkeley
pp. 302
Hai Zhou , University of Texas at Austin
D. F. Wong , University of Texas at Austin
pp. 310
J.G. Xi , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 316
Session 5D: BIST and DFT, Moderators: Yervant Zorian, Robert C. Aitken
Frank F. Hsu , University of Illinois
Elizabeth M. Rudnick , University of Illinois
Janak H. Patel , University of Illinois
pp. 322
Bit-Flipping BIST (Abstract)
Hans-Joachim Wunderlich , University of Stuttgart, Germany
pp. 337
Session 6A: Formal Verification II, Moderators: Fabio Somenzi, Ellen M. Sentovich
Aarti Gupta , CCRL, NEC
Sharad Malik , Princeton University
pp. 346
Gianpiero Cabodi , Politecnico di Torino
Stefano Quer , Politecnico di Torino
Paolo Camurati , Politecnico di Torino
pp. 354
Yirng-An Chen , Carnegie Mellon University
Randal E. Bryant , Carnegie Mellon University
pp. 361
Session 6B: Yield and Technology Modeling, Moderators: Jacob K. White, David Ling
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
Eric Felt , University of California, Berkeley
Carlo Guardiani , SGS-Thomson Microelectronics
pp. 374
W. Hong , Dept. of Radio Eng., Southeast Univ., Nanjing, China
W. Sun , Dept. of Radio Eng., Southeast Univ., Nanjing, China
Z. Zhu , Dept. of Radio Eng., Southeast Univ., Nanjing, China
H. Ji , Dept. of Radio Eng., Southeast Univ., Nanjing, China
B. Song , Dept. of Radio Eng., Southeast Univ., Nanjing, China
W. Wei-Ming Dai , Dept. of Radio Eng., Southeast Univ., Nanjing, China
pp. 381
Session 6C: Topics in Power and Timing Analysis, Moderators: Thomas G. Szymanski, Murray Hill
Daniel Brand , IBM T.J. Watson Research Center
pp. 388
Hien Ha , University of California, Santa Barbara
Forrest Brewer , University of California, Santa Barbara
Ashok Vittal , Silicon Graphics Inc.
pp. 395
Wen-Zen Shen , National Chiao Tung Univ.
Jiing-Yuan Lin , National Chiao Tung Univ.
pp. 400
Session 6D: Verification and Fault Tolerance, Moderators: Kunle Olukotun, Steve Tjiang
William J. Schilp , University of South Florida
Peter M. Maurer , University of South Florida
pp. 412
Session 7A: Extending the Scope of High-Level Synthesis, Moderators: Don MacMillen, Yuon-Long Lin
Ellen M. Sentovich , Ecole Nationale Superieure des Mines de Paris
Gerard Berry , Ecole Nationale Superieure des Mines de Paris
pp. 428
Ki-Seok Chung , University of Illinois at Urbana-Champaign
C.L. Liu , University of Illinois at Urbana-Champaign
pp. 442
Session 7B: Analog CAD and Methodology, Moderators: Georges Gielen, John Cohn
Jonathan Fowler , Georgia Institute of Technology
Paul Kerstetter , Georgia Institute of Technology
Giorgio Casinovi , Georgia Tech Research Institute
pp. 450
Ranjit Gharpurey , Texas Instruments Inc.
Edoardo Charbon , Cadence Design Systems Inc.
Alberto Sangiovanni-Vincentelli , University of California, Berkeley, CA
pp. 455
Alper Demir , University of California, Berkeley
Paolo Miliozzi , University of California, Berkeley
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
Iasson Vassiliou , University of California, Berkeley
Edoardo Charbon , Cadence Design Systems, Inc.
pp. 463
Session 7C: Partitioning and Floorplan, Moderators: Martin D.F. Wong, Frank M. Johannes
Klaus Harbich , University of Hanover
Dirk Behrens , University of Hanover
pp. 470
Takayuki Yamanouchi , Sharp Corporation
Kazuo Tamakashi , Sharp Corporation
Takashi Kambe , Sharp Corporation
pp. 478
Yoji Kajitani , Tokyo Institute of Technology
Shigetoshi Nakatake , Tokyo Institute of Technology
Hiroshi Murata , Japan Advanced Institute of Science and Technology (JAIST)
pp. 484
Session 7D: Delay Fault Test, Moderators: E.J. McCluskey, Ray Mercer
Keerthi Heragu , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
pp. 502
Session 8A: Embedded Tutorial, Presenter: Gordon W. Roberts
G.W. Roberts , Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
pp. 514
Session 8B: Embedded Tutorial, Presenters: Ken L. Shepard, Vinod Narayanan
Kenneth L. Shepard , IBM T. J. Watson Research Center
pp. 524
Session 9A: Panel
Session 10A: BDD Applications and Techniques, Moderators: Albert Wang, Sujit Dey
Scott Woods , Georgia Institute of Technology
pp. 542
A. Narayan , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
J. Jain , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
M. Fujita , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 547
Session 10B: Advances in Transmission Line Analysis, Moderators: Chandu Visweswariah, Rob A. Rutenbar
Janet Meiling Wang , University of California at Berkeley
Jun-Fa Mao , University of California at Berkeley
pp. 556
Sharad Kapur , Lucent Technologies
David E. Long , Lucent Technologies
Jaijeet Roychowdhury , Lucent Technologies
pp. 569
Session 1OC: Power and Current Modeling, Moderators: Farid N. Najm, Jyuo-Min Shyu
Qing Wu , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Chih-Shun Ding , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 583
Session 10D: Mixed-Signal Testing, Moderators: Ranga Vemuri, Gordon Roberts
Yue-Tsang Chen , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Shyh-Jye Jou , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Chanchin Su , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 594
Leandro Pulz , DELET/UFRGS
Marcelo Lubaszewski , DELET/UFRGS
pp. 600
Walter M. Lindermeir , Institute of Electronic Design Automation
pp. 604
Session 11A: Logic Synthesis, Moderators: Narendra Shenoy, Carl Pixley
Balakrishnan Iyer , University of Massachusetts at Amherst
Maciej Ciesielski , University of Massachusetts at Amherst
pp. 614
Sharad Malik , Princeton University
Vigyan Singhal , Cadence Berkeley Labs
pp. 618
Session 11B: System Level Optimization and Validation, Moderators: P.A. Subrahmanyam, Masaharu Imai
I. Hong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Potkonjak , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 634
Shin-ichi Minato , NTT System Electronics Laboratories
pp. 644
Session 11C: Special Topics In Physical Design, Moderators: Dwight Hill, Atushi Takahashi
Vaughn Betz , University of Toronto
Jonathan Rose , University of Toronto
pp. 652
J. Darnauer , Board of Studies in Comput. Eng., California Univ., Santa Cruz, CA, USA
Man-Fai Yu , Board of Studies in Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 668
Session 11D: Fault Diagnosis, Moderators: Rabindra K. Roy, Justin Harlow
X. T. Chen , Texas A&M University
F. Lombardi , Texas A&M University
pp. 676
V. Boppana , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 681
K. Chakraborty , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
P. Mazumder , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 685
Session 12A: Embedded Tutorial, Presenters: W. Maly, H. Heineken, J. Khare, P.K. Nag
H. Heineken , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
P.K. Nag , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 690
Session 12B: Embedded Tutorial, Presenter: L.P.P.P. van Ginneken, N.V. Shenoy, R.H.J.M. Otten
Author Index (PDF)
pp. 703
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