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1995 International Conference on Computer-Aided Design (ICCAD '95)
San Jose, CA
November 05-November 09
ISBN: 0-8186-7213-7
Table of Contents
Session 1A: Formal Verification, Moderators: Ellen M. Sentovich, Sophia Antipolis, David E. Long
Robert B. Jones, Computer Systems Laboratory
David L. Dill, Computer Systems Laboratory
Jerry R. Burch, Cadence Berkeley Laboratories
pp. 0002
Session 1B: Power Analysis, Moderators: Farid N. Najm, Sharad Malik
Peter A. Beerel, University of Southern California
Pei-Chuan Yeh, University of Southern California
Kenneth Y. Yun, University of California, San Diego
Steven M. Nowick, Columbia University
pp. 0026
T.-L. Chou, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 0034
Session 1C: Interconnect Modeling, Moderators: David Ling, Keith Nabors
M. Chou, Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. White, Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 0040
R. Achar, Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
M.S. Nakhla, Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Q.J. Zhang, Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
pp. 0053
Session 1D: Issues in Clock Design, Moderators: M. Marek-Sadowska, Ren-Song Tsay
Gustavo E. Tellez, Northwestern University
Amir Farrahi, Northwestern University
Majid Sarrafzadeh, Northwestern University
pp. 0062
Jason Cong, UCLA Dept. of Computer Science
Andrew B. Kahng, UCLA Dept. of Computer Science
Cheng-Kok Koh, UCLA Dept. of Computer Science
C.-W. Albert Tsao, UCLA Dept. of Computer Science
pp. 0066
Session 2A: DCs and DDs in Logic Synthesis, Moderators: Michel Berkelaar, Sujit Dey
D. Brand, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R.A. Bergamaschi, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
L. Stok, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 0083
Session 2B: Advances in BIST, Moderators: Yervant Zorian, Sandeep Gupta
Sybille Hellebrand, University of Siegen, Germany
Birgit Reeb, University of Siegen, Germany
Hans-Joachim Wunderlich, University of Siegen, Germany
Steffen Tarnick, Max-Planck Society, University of Potsdam
pp. 0088
Chen-Yang Pan, University of California, Santa Barbara
Kwang-Ting Cheng, University of California, Santa Barbara
pp. 0102
Session 2C: New Directions in Circuit Simulation and Verification, Moderators: Peter Feldmann, Andrew T. Yang
D. Zhou, University of North Carolina at Charlotte
N. Chen, University of North Carolina at Charlotte
W. Cai, The University of California, Santa Barbara
pp. 0115
Session 2D: Interconnect Optimization, Moderators: Jason Kong, Georges Gielen
John Lillis, University of California, San Diego
Chung-Kuan Cheng, University of California, San Diego
Ting-Ting Y. Lin, University of California, San Diego
pp. 0138
Noel Menezes, The University of Texas at Austin
Ross Baldick, The University of Texas at Austin
Lawrence T. Pileggi, The University of Texas at Austin
pp. 0144
Session 3A: Decision Diagrams: Applications and Extensions, Moderators: Olivier Coudert, Srinivas Devadas
Kavita Ravi, University of Colorado at Boulder
Fabio Somenzi, University of Colorado at Boulder
pp. 0154
E.M. Clarke, Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
M. Fujita, Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
X. Zhao, Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 0159
Jordi Cortadella, Universitat Politecnica de Catalunya
Michael Kishinevsky, The University of Aizu
Luciano Lavagno, Politecnico di Torino
Alex Yakovlev, University of Newcastle upon Tyne
pp. 0164
Session 3B: Fault and Error Diagnosis, Moderators: Wolfgang Kunz, Dhiraj K. Pradhan
Yiming Gong, State University of New York
Sreejit Chakravarty, State University of New York
pp. 0181
B. Chess, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
D.B. Lavo, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
F.J. Ferguson, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
T. Larrabee, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 0185
Session 3C: Substrate Coupling, Moderators: Jue-Hsien Chern, Jacob K. White
T. Smedes, Delft University of Technology
N.P. van der Meijs, Delft University of Technology
A.J. Van Genderen, Delft University of Technology
pp. 0199
Session 3D: Circuit Partitioning, Moderators: Jason Cong, Frank M. Johannes
H.H. Yang, Intel Corp., Hillsboro, OR, USA
D.F. Wong, Intel Corp., Hillsboro, OR, USA
pp. 0216
Jianmin Li, University of California, San Diego
John Lillis, University of California, San Diego
Chung-Kuan Cheng, University of California, San Diego
pp. 0223
Lung-Tien Liu, AT&T Bell Laboratories
Ming-Ter Kuo, University of California, San Diego
Chung-Kuan Cheng, University of California, San Diego
Shih-Chen Huang, New York University
pp. 0229
Session 4A: Embedded Tutorial, Moderator: Gary Hachtel
Session 4B: Embedded Tutorial, Moderator: John Cohn
Session 5A: Advances in Logic Synthesis, Moderators: Robert Brayton, Gary Hachtel
Eric Lehman, Digital Equipment Corporation
Yosinori Watanabe, Digital Equipment Corporation
Joel Grodstein, Digital Equipment Corporation
Heather Harkness, Digital Equipment Corporation
pp. 0264
Reinaldo A. Bergamaschi, IBM T. J. Watson Research Center
Daniel Brand, IBM T. J. Watson Research Center
Leon Stok, IBM T. J. Watson Research Center
Michel Berkelaar, Eindhoven University of Technology
Shiv Prakash, Mentor Graphics Corp.
pp. 0272
Session 5B: System Integration and Debugging, Moderators: Luciano Lavagno, Paul Lippens
Pai Chou, Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
R.B. Ortega, Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
G. Borriello, Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 0280
Ti-Yen Yen, Quickturn Design Syst. Inc., Mountain View, CA, USA
W. Wolf, Quickturn Design Syst. Inc., Mountain View, CA, USA
pp. 0288
M. Potkonjak, C&C Res. Labs., NEC USA, Princeton, NJ, USA
S. Dey, C&C Res. Labs., NEC USA, Princeton, NJ, USA
K. Wakabayashi, C&C Res. Labs., NEC USA, Princeton, NJ, USA
pp. 0295
Session 5C: Test Generation and Synthesis for Test, Moderators: Fadi Maamari, Irith Pomeranz
M. Chatterjee, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D.K. Pradhan, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
W. Kunz, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 0318
Session 5D: FPGA Routing, Moderators: Dwight Hill, Y. Kajitani
S.K. Nag, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 0332
, Moderators: Session 6A: FPGA Synthesis, Moderators: Bob Francis, Albert Wang
Hiroshi Sawada, NTT Communication Science Laboratories
Takayuki Suyama, NTT Communication Science Laboratories
Akira Nagoya, NTT Communication Science Laboratories
pp. 0353
Juinn-Dar Huang, National Chiao Tung University
Jing-Yang Jou, National Chiao Tung University
Wen-Zen Shen, National Chiao Tung University
pp. 0359
Session 6B: Circuit Path Analysis in Timing and Power, Moderators: Tom Szymanski, Alexander Saldanha
Chin-Chi Teng, University of Illinois at Urbana-Champaign
Anthony M. Hill, University of Illinois at Urbana-Champaign
Sung-Mo Kang, University of Illinois at Urbana-Champaign
pp. 0366
Session 6C: Code Generation and Performance Estimation, Moderators: Hiroto Yasuura, Wayne Wolf
Session 6D: Discrete Simulation, Moderators: Steve Tjiang, Robert French
P. Ashar, CCRL, NEC USA, Princeton, NJ, USA
S. Malik, CCRL, NEC USA, Princeton, NJ, USA
pp. 0408
Session 7A: Power and Delay Optimization in Synthesis, Moderators: Sujit Dey, Michel Berkelaar
S. Iman, Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram, Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 0433
Session 7B: System-Level Partitioning Issues, Moderators: Jef Van Meerbergen, Rajesh Gupta
A.H. Farrahi, Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
M. Sarrafzadeh, Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
pp. 0452
Session 7C: Gate Sizing, Moderators: Hidetoshi Onodera, Patrick McGeer
J. Grodstein, Digital Equipment Corp., Hudson, MA, USA
E. Lehman, Digital Equipment Corp., Hudson, MA, USA
H. Harkness, Digital Equipment Corp., Hudson, MA, USA
B. Grundmann, Digital Equipment Corp., Hudson, MA, USA
Y. Watanabe, Digital Equipment Corp., Hudson, MA, USA
pp. 0458
S.S. Sapatnekar, Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Weitong Chuang, Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 0463
H. Sathyamurthy, Mentor Graphics, San Jose, CA, USA
S.S. Sapatnekar, Mentor Graphics, San Jose, CA, USA
J.P. Fishburn, Mentor Graphics, San Jose, CA, USA
pp. 0467
Session 7D: Floorplanning and Placement, Moderators: Takashi Kambe, Ralph Otten
H. Murata, Japan Advanced Institute of Science and Technology (JAIST)
K. Fujiyoshi, Japan Advanced Institute of Science and Technology (JAIST)
S. Nakatake, Japan Advanced Institute of Science and Technology (JAIST)
Y. Kajitani, Tokyo Institute of Technology (Titech)
pp. 0472
A. Mathur, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
K.C. Chen, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
C.L. Liu, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 0485
Session 8A Embedded Tutorial, Moderator: Sharad Malik
Session 8B: Embedded Tutorial, Moderator: Wayne Wolf
P. Lippens, Philips Res. Lab., Eindhoven, Netherlands
V. Nagasamy, Philips Res. Lab., Eindhoven, Netherlands
W. Wolf, Philips Res. Lab., Eindhoven, Netherlands
pp. 0502
Session 9A: Memory System Design, Moderators: Nikil Dutt, Don MacMillan
Wei Zhao, Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
C.A. Papachristou, Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 0521
Session 9B: Novel Views on DFT, Moderators: Wojciech Maly, John P. Hayes
Chih-chang Lin, University of California, Santa Barbara
Malgorzata Marek-Sadowska, University of California, Santa Barbara
Mike Tien-Chien Lee, Fujitsu Laboratories of America, Inc.
Kuang-Chien Chen, Fujitsu Laboratories of America, Inc.
pp. 0528
Sujit Dey, C&C Research Laboratories, NEC USA
Vijay Gangaram, C&C Research Laboratories, NEC USA
Miodrag Potkonjak, C&C Research Laboratories, NEC USA
pp. 0534
Session 9C: Analog CAD, Moderators: Rob A. Rutenbar, Kurt J. Antreich
Jan Crols, Katholieke Universiteit Leuven, ESAT-MICAS
Steaphane Donnay, Katholieke Universiteit Leuven, ESAT-MICAS
Michiel Steyaert, Katholieke Universiteit Leuven, ESAT-MICAS
Georges Gielen, Katholieke Universiteit Leuven, ESAT-MICAS
pp. 0550
S.R. Kadivar, Res. & Dev., Siemens AG, Munich, Germany
D. Schmitt-Landsiedel, Res. & Dev., Siemens AG, Munich, Germany
H. Klar, Res. & Dev., Siemens AG, Munich, Germany
pp. 0554
E.J. Peralias, (CNM), University of Seville
A. Rueda, (CNM), University of Seville
J.L. Huertas, (CNM), University of Seville
pp. 0562
Session 9D: Optimization of Interconnects, Moderators: Majid Sarrafzadeh, Andrew B. Kahng
Jason Cong, University of California, Los Angeles, CA
Lei He, University of California, Los Angeles, CA
pp. 0568
Man-Fai Yu, University of California, Santa Cruz,
Wayne Wei-Ming Dai, University of California, Santa Cruz,
pp. 0581
Session 10A: Advanced Scheduling Techniques, Moderators: Wolfgang Rosenstiel, Yukihiro Nakamura
Fermin Sanchez, Univ. Politecnica de Catalunya, Barcelona (Spain)
Jordi Cortadella, Univ. Politecnica de Catalunya, Barcelona (Spain)
pp. 0592
Session 10B: Sequential Synthesis, Moderators: Luciano Lavagno, Pabio Somenzi
Adnan Aziz, University of California at Berkeley
Felice Balarin, University of California at Berkeley
Robert K. Brayton, University of California at Berkeley
Alberto Sangiovanni-Vincentelli, University of California at Berkeley
pp. 0612
Huey-Yih Wang, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 0728
Session 10C: Analog Testing, Moderators: Peter C. Maxwell, Kwang-Ting Cheng
Walter M. Lindermeir, Technical University of Munich
Helmut E. Graeb, Technical University of Munich
Kurt J. Antreich, Technical University of Munich
pp. 0620
Session 10D: Partitioning for Performance and Power, Moderators: Rajeev Jayaraman, Andrew B. Kahng
H. Vaishnav, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 0638
David Ihsin Cheng, University of California, Santa Barbara
Chih-chang Lin, University of California, Santa Barbara
Malgorzata Marek-Sadowska, University of California, Santa Barbara
pp. 0650
Session 11A: New Objectives in High Level Synthesis, Moderators: Youn-Long Lin, Reinaldo Bergamaschi
B. Iyer, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
R. Karri, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 0658
Elof Frank, GMD -- German National Research Center for Information Technology
Thomas Lengauer, GMD -- German National Research Center for Information Technology
pp. 0662
M. Mehendale, Texas Instrum. (India) Ltd., Bangalore, India
S.D. Sherlekar, Texas Instrum. (India) Ltd., Bangalore, India
G. Venkatesh, Texas Instrum. (India) Ltd., Bangalore, India
pp. 0668
Session 11B: Fault Simulation and Delay Testing, Moderators: Janak H. Patel, Chen-Shang Lin
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 0687
Session 11C: Circuit Models and TCAD, Moderators: Sani Nassig, Jacob K. White
Session 11D: Floorplanning and Placement Algorithms, Moderators: Majid Sarrafiadeh, Ralph Otten
Jaewon Kim, University of Illinois at Urbana-Champaign
S. M. Kang, University of Illinois at Urbana-Champaign
pp. 0716
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