Most existing performance-driven and clock routing algorithms construct optimal routing topology for each net individually without considering its routability on the chip, so they can not guarantee performance after all nets are routed. This paper proposes a new approach for post routing performance optimization via multi-link insertion and non-uniform wiresizing, which improves the performance of a net topology obtained from a global routing solution. Unlike previous approaches, it can achieve reduction in both maximum delay and skew to satisfy user specified constraints and minimizes the routing resource consumed. During optimization, the topology of the net is kept routable. Experiments show that link insertion and wiresizing can improve net performance significantly, and among all approaches, multi-link insertion and wiresizing achieves the best performance and area efficiency.