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1995 International Conference on Computer-Aided Design (ICCAD '95)
Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques
San Jose, CA
November 05-November 09
ISBN: 0-8186-7213-7
| ASCII Text | x | ||
| M. Potkonjak, W. Wolf, "Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques," Computer-Aided Design, International Conference on, pp. 0446, 1995 International Conference on Computer-Aided Design (ICCAD '95), 1995. | |||
| BibTex | x | ||
| @article{ 10.1109/ICCAD.1995.480154, author = {M. Potkonjak and W. Wolf}, title = {Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques}, journal ={Computer-Aided Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-7213-7}, pages = {0446}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCAD.1995.480154}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Computer-Aided Design, International Conference on TI - Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques SN - 0-8186-7213-7 SP EP A1 - M. Potkonjak, A1 - W. Wolf, PY - 1995 KW - high level synthesis; logic design; application specific integrated circuits; real-time systems; circuit optimisation; circuit CAD; cost optimization; ASIC implementation; periodic hard-real time systems; behavioral synthesis techniques; synthesis algorithm; multiple computational tasks; task sharing; datapath synthesis criteria; rate-monotonic scheduling; allocation algorithms; multiple-task examples VL - 0 JA - Computer-Aided Design, International Conference on ER - | |||
Abstract: Modern applications are often defined as sets of several computational tasks. This paper presents a synthesis algorithm for ASIC implementations which realize multiple computational tasks under hard real-time deadlines. The algorithm analyzes constraints imposed by task sharing as well as the traditional datapath synthesis criteria. In particular we demonstrated an efficient technique to combine rate-monotonic scheduling, a widely used hard real-time systems scheduling discipline, with estimations and scheduling and allocation algorithms. Matching the number of bits in tasks assigned to the same processor was the most important factor in obtaining good designs. We have demonstrated the effectiveness of our algorithms on several multiple-task examples.
Index Terms:
high level synthesis; logic design; application specific integrated circuits; real-time systems; circuit optimisation; circuit CAD; cost optimization; ASIC implementation; periodic hard-real time systems; behavioral synthesis techniques; synthesis algorithm; multiple computational tasks; task sharing; datapath synthesis criteria; rate-monotonic scheduling; allocation algorithms; multiple-task examples
Citation:
M. Potkonjak, W. Wolf, "Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques," iccad, pp.0446, 1995 International Conference on Computer-Aided Design (ICCAD '95), 1995
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