Program Chairs' message

list-reviewer (PDF)

pp. xi

General Co-Chairs’ Message (PDF)

pp. ix

Keynote I

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Microarchitecture: Are We Finally Done?

Session 1: Power Management

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Exploiting Prediction to Reduce Power on Buses (Abstract)

Victor Wen, University of California at Berkeley

Mark Whitney, University of California at Berkeley

Yatish Patel, University of California at Berkeley

John D. Kubiatowicz, University of California at Berkeley

pp. 2

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The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors (Abstract)

Jian Li, Cornell University

José F. Martínez, Cornell University

Michael C. Huang, University of Rochester

pp. 14

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Program Counter Based Techniques for Dynamic Power Management (Abstract)

Chris Gniady, Purdue University

Y Charlie Hu, Purdue University

Yung-Hsiang Lu, Purdue University

pp. 24

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Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization (Abstract)

Russ Joseph, Princeton University

Zhigang Hu, IBM Corporation

Margaret Martonosi, Princeton University

pp. 36

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Session 2: Processor Design I

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Out-of-Order Commit Processors (Abstract)

Adrian Cristal, Universidad Politécnica de Cataluña

Daniel Ortega, Hewlett Packard Labs

Josep Llosa, Universidad Politécnica de Cataluña

Mateo Valero, Universidad Politécnica de Cataluña

pp. 48

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Stream Register Files with Indexed Access (Abstract)

Nuwan Jayasena, Stanford University

Mattan Erez, Stanford University

Jung Ho Ahn, Stanford University

William J. Dally, Stanford University

pp. 60

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Low-Complexity Distributed Issue Queue (Abstract)

Jaume Abella, Universitat Polit?cnica de Catalunya

Antonio Gonz?lez, Universitat Polit?cnica de Catalunya and Intel Barcelona Research Center

pp. 73

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Session 3: Prefetching

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Hardware Support for Prescient Instruction Prefetch (Abstract)

Tor M. Aamodt, University of Toronto

Paul Chow, University of Toronto

Per Hammarlund, Intel Corporation

Hong Wang, Intel Corporation

John P. Shen, Intel Corporation

pp. 84

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Data Cache Prefetching Using a Global History Buffer (Abstract)

Kyle J. Nesbit, University of Wisconsin - Madison

James E. Smith, University of Wisconsin - Madison

pp. 96

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Processor Aware Anticipatory Prefetching in Loops (Abstract)

Spiros Kalogeropulos, Sun Microsystems, Inc.

Mahadevan Rajagopalan, Sun Microsystems, Inc.

Vikram Rao, Sun Microsystems, Inc.

Yonghong Song, Sun Microsystems, Inc.

Partha Tirumalai, Sun Microsystems, Inc.

pp. 106

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Panel Session:

Bridging the Research Gap between Academia and Industry

Keynote II

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Designing for the High End

Session 4: I/O

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Reducing Energy Consumption of Disk Storage Using Power-Aware Cache Management (Abstract)

Qingbo Zhu, University of Illinois at Urbana Champaign

Francis M. David, University of Illinois at Urbana Champaign

Christo F. Devaraj, University of Illinois at Urbana Champaign

Zhenmin Li, University of Illinois at Urbana Champaign

Yuanyuan Zhou, University of Illinois at Urbana Champaign

Pei Cao, Cisco Systems Inc.

pp. 118

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Improving Disk Throughput in Data-Intensive Servers (Abstract)

Enrique V. Carrera, Rutgers University

Ricardo Bianchini, Rutgers University

pp. 130

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Synthesizing Representative I/O Workloads for TPC-H (Abstract)

Jianyong Zhang, Pennsylvania State University

Anand Sivasubramaniam, Pennsylvania State University

Hubertus Franke, IBM T. J. Watson Research Center

Natarajan Gautam, Pennsylvania State University

Yanyong Zhang, Rutgers University

Shailabh Nagar, IBM T. J. Watson Research Center

pp. 142

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Architectural Characterization of TCP/IP Packet Processing on the Pentium? M Microprocessor (Abstract)

Srihari Makineni, Intel Corporation

Ravi Iyer, Intel Corporation

pp. 152

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Session 5: Caches & Memory I

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Signature Buffer: Bridging Performance Gap between Registers and Caches (Abstract)

Lu Peng, University of Florida

Jih-Kwon Peir, University of Florida

Konrad Lai, Intel Corporation

pp. 164

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Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs (Abstract)

Chun Liu, Pennsylvania State University

Anand Sivasubramaniam, Pennsylvania State University

Mahmut Kandemir, Pennsylvania State University

pp. 176

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Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration (Abstract)

Pierre Michaud, IRISA/INRIA

pp. 186

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Keynote III

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Kilo-Instructions In-Flight Processors

Session 6: Scheduling

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Understanding Scheduling Replay Schemes (Abstract)

Ilhyun Kim, University of Wisconsin-Madison

Mikko H. Lipasti, University of Wisconsin-Madison

pp. 198

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Creating Converged Trace Schedules Using String Matching (Abstract)

Satish Narayanasamy, University of California at San Diego

Yuanfang Hu, University of California at San Diego

Suleyman Sair, North Carolina State University

Brad Calder, University of California at San Diego

pp. 210

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Reducing the Scheduling Critical Cycle Using Wakeup Prediction (Abstract)

Todd E. Ehrhart, University of Illinois at Urbana-Champaign

Sanjay J. Patel, University of Illinois at Urbana-Champaign

pp. 222

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Exploring Wakeup-Free Instruction Scheduling (Abstract)

Jie S. Hu, Pennsylvania State University

N. Vijaykrishnan, Pennsylvania State University

Mary Jane Irwin, Pennsylvania State University

pp. 232

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Keynote IV

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POWER5 Architecture and Systems

Session 7: Processor Design II

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A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors (Abstract)

Ayose Falcón, Universitat Politècnica de Catalunya

Alex Ramirez, Universitat Politècnica de Catalunya

Mateo Valero, Universitat Politècnica de Catalunya

pp. 244

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Reducing Branch Misprediction Penalty via Selective Branch Recovery (Abstract)

Amit Gandhi, Intel Corporation and Portland State University

Haitham Akkary, Intel Corporation and Portland State University

Srikanth T. Srinivasan, Intel Corporation

pp. 254

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Perceptron-Based Branch Confidence Estimation (Abstract)

Haitham Akkary, Portland State University and Intel Corporation

Srikanth T. Srinivasan, Intel Corporation

Rajendar Koltur, Portland State University

Yogesh Patil, Portland State University

Wael Refaai, Portland State University

pp. 265

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Session 8: Caches & Memory II

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Accurate and Complexity-Effective Spatial Pattern Prediction (Abstract)

Chi F. Chen, Carnegie Mellon University

Se-Hyun Yang, Carnegie Mellon University

Babak Falsafi, Carnegie Mellon University

Andreas Moshovos, University of Toronto

pp. 276

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Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses (Abstract)

Mazen Kharbutli, North Carolina State University

Keith Irwin, North Carolina State University

Yan Solihin, North Carolina State University

Jaejin Lee, Seoul National University

pp. 288

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Link-Time Path-Sensitive Memory Redundancy Elimination (Abstract)

Manel Fernández, Universitat Politècnica de Catalunya

Roger Espasa, Universitat Politècnica de Catalunya

pp. 300

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Author Index

Author Index (PDF)

pp. 311