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10th International Symposium on High Performance Computer Architecture (HPCA'04)
Signature Buffer: Bridging Performance Gap between Registers and Caches
Madrid, Spain
February 14-February 18
ISBN: 0-7695-2053-7
| ASCII Text | x | ||
| Lu Peng, Jih-Kwon Peir, Konrad Lai, "Signature Buffer: Bridging Performance Gap between Registers and Caches," High-Performance Computer Architecture, International Symposium on, pp. 164, 10th International Symposium on High Performance Computer Architecture (HPCA'04), 2004. | |||
| BibTex | x | ||
| @article{ 10.1109/HPCA.2004.10020, author = {Lu Peng and Jih-Kwon Peir and Konrad Lai}, title = {Signature Buffer: Bridging Performance Gap between Registers and Caches}, journal ={High-Performance Computer Architecture, International Symposium on}, volume = {0}, year = {2004}, issn = {1530-0897}, pages = {164}, doi = {http://doi.ieeecomputersociety.org/10.1109/HPCA.2004.10020}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - High-Performance Computer Architecture, International Symposium on TI - Signature Buffer: Bridging Performance Gap between Registers and Caches SN - 1530-0897 SP EP A1 - Lu Peng, A1 - Jih-Kwon Peir, A1 - Konrad Lai, PY - 2004 KW - null VL - 0 JA - High-Performance Computer Architecture, International Symposium on ER - | |||
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new storage media with a novel addressing mechanism to avoid address calculations. Instead of a memory address, each load and store is assigned a signature for accessing the new storage. A signature consists of the color of the base register along with its displacement value. A unique color is assigned to a register whenever the register is updated. When two memory instructions have the same signature, they address to the same memory location. This memory signature can be formed early in the processor pipeline. A small Signature Buffer, addressed by the memory signature, can be established to permit stores and loads bypassing normal memory hierarchy for fast data communication. Performance evaluations based on an Alpha 21264-like pipeline using SPEC2000 integer benchmarks show that an IPC (Instruction-Per-Cycle) improvement of 13-18% is possible using a small 8-entry signature buffer.
Citation:
Lu Peng, Jih-Kwon Peir, Konrad Lai, "Signature Buffer: Bridging Performance Gap between Registers and Caches," hpca, pp.164, 10th International Symposium on High Performance Computer Architecture (HPCA'04), 2004
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