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3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97)
San Antonio, TX
February 01-February 05
ISBN: 0-8186-7764-3
Table of Contents
Session I-A: Novel Memory Architecture
Liuxi Yang, Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, IL
Josep Torrellas, Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, IL
pp. 4
A. Wolfe, Dept. of Electr. Eng., Princeton Univ., NJ, USA
J. Fritts, Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Dutta, Dept. of Electr. Eng., Princeton Univ., NJ, USA
E.S.T Fernandes, Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 24
Session I-B: Routing and Networks
X. Yuan, Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
R. Melhem, Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
R. Gupta, Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
pp. 38
Ram Kesavan, The Ohio State University, Columbus, OH
Kiran Bondalapati, The Ohio State University, Columbus, OH
Dhabaleswar K. Panda, The Ohio State University, Columbus, OH
pp. 48
Govindan Ravindran, Department of Electrical and Computer Engineering University of Toronto
Michael Stumm, Department of Electrical and Computer Engineering University of Toronto
pp. 58
Session II-A: ILP and Branch Handling
David I. August, University of Illinois, Urbana-Champaign, IL
Daniel A. Connors, University of Illinois, Urbana-Champaign, IL
John C. Gyllenhaal, University of Illinois, Urbana-Champaign, IL
Wen-mei W. Hwu, University of Illinois, Urbana-Champaign, IL
pp. 84
Steven Wallace, University of California, Irvine
Nader Bagherzadeh, University of California, Irvine
pp. 94
Session II-B: Efficient Communications
Kai Hwang, The University of Hong Kong, Pokfulam, Hong Kong
Choming Wang, The University of Hong Kong, Pokfulam, Hong Kong
Cho-Li Wang, The University of Hong Kong, Pokfulam, Hong Kong
pp. 106
B-H. Lim, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
P. Heidelberger, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
P. Pattnaik, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
M. Snir, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 116
Babak Falsafi, University of Wisconsin - Madison
David A. Wood, University of Wisconsin - Madison
pp. 128
Panel Session: Shared-Memory Multiprocessors
Session III-A: Memory Systems
B. Jacob, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
T. Mudge, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 156
T. Stricker, Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
T. Cross, Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 168
Session III-B: Communication-Efficient Cache Architectures
Session IV-A: High-Performance Processors
Quinn Jacobson, University of Wisconsin - Madison
Steve Bennett, University of Wisconsin - Madison
Nikhil Sharma, University of Wisconsin - Madison
James E. Smith, University of Wisconsin - Madison
pp. 218
Roger Espasa, Universitat Politecnica Catalunya, Barcelona
Mateo Valero, Universitat Politecnica Catalunya, Barcelona
pp. 237
Session IV-B: Shared-Memory Multiprocessors
Zheng Zhang, University of Illinois at Urbana-Champaign, IL
Josep Torrellas, University of Illinois at Urbana-Champaign, IL
pp. 272
Panel Session: Computer Architecture Research for a New Century
Session V-A: Performance Evaluation and Characterization
Sucheta Chodnekar, The Pennsylvania State University
Viji Srinivasan, The Pennsylvania State University
Aniruddha S. Vaidya, The Pennsylvania State University
Anand Sivasubramaniam, The Pennsylvania State University
Chita R. Das, The Pennsylvania State University
pp. 310
Session V-B: Network Interface
Evangelos P. Markatos, Institute of Computer Science (ICS) Foundation for Research & Technology -- Hellas (FORTH)
Manolis G.H. Katevenis, Institute of Computer Science (ICS) Foundation for Research & Technology -- Hellas (FORTH)
pp. 322
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