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2nd IEEE Symposium on High-Performance Computer Architecture (HPCA '96)
San Jose, CA
February 03-February 07
ISBN: 0-8186-7237-4
Table of Contents
Session I-A: Network of Workstations
Liviu Iftode, Department of Computer Science Princeton University
Cezary Dubnicki, Department of Computer Science Princeton University
Edward W. Felten, Department of Computer Science Princeton University
Kai Li, Department of Computer Science Princeton University
pp. 14
Session I-B: Instruction Scheduling
Vijay S. Iyengar, IBM Research Division Thomas J. Watson Research Center
Louise H. Trevillyan, IBM Research Division Thomas J. Watson Research Center
Pradip Bose, IBM Research Division Thomas J. Watson Research Center
pp. 62
Session II-A: Shared-Memory Multiprocessors
B.A. Nayfeh, Comput. Syst. Lab., Stanford Univ., CA, USA
K. Olukotun, Comput. Syst. Lab., Stanford Univ., CA, USA
J.P. Singh, Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 74
Chun Xia, Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
Josep Torrellas, Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
pp. 85
A. Landin, Swedish Inst. of Comput. Sci., Kista, Sweden
F. Dahlgren, Swedish Inst. of Comput. Sci., Kista, Sweden
pp. 95
Session II-B: Interconnection Networks
H. ElGindy, The University of Newcastle
A. K. Somani, University of Washington
H. Schroder, Loughborough University of Technology Loughborough
H. Schmeck, Universitat Karlsruhe
A. Spray, The University of Newcastle
pp. 108
Chunming Qiao, Department of Electrical and Computer Engineering State University of New York at Buffalo
Yousong Mei, Department of Electrical and Computer Engineering State University of New York at Buffalo
pp. 118
Session III-A: Network Interfaces
Evangelos P. Markatos, Institute of Computer Science (ICS) Foundation for Research & Technology -- Hellas (FORTH)
Manolis G.H. Katevenis, Institute of Computer Science (ICS) Foundation for Research & Technology -- Hellas (FORTH)
pp. 144
M.A. Blumrich, Dept. of Comput. Sci., Princeton Univ., NJ, USA
C. Dubnicki, Dept. of Comput. Sci., Princeton Univ., NJ, USA
E.W. Felten, Dept. of Comput. Sci., Princeton Univ., NJ, USA
Kai Li, Dept. of Comput. Sci., Princeton Univ., NJ, USA
pp. 154
L.I. Kontothanassis, Dept. of Comput. Sci., Rochester Univ., NY, USA
M.L. Scott, Dept. of Comput. Sci., Rochester Univ., NY, USA
pp. 166
Session III-B: Network Routing
Session IV-A: Multiprocessor Systems
Henk L. Muller, Department of Computer Science, University of Bristol, UK. Working at: Partnership in Advanced Computing Technologies Science Research Foundation, 10 Priory Road, Bristol. BS8 1TU, UK.
Paul W.A. Stallard, Department of Computer Science, University of Bristol, UK. Working at: Partnership in Advanced Computing Technologies Science Research Foundation, 10 Priory Road, Bristol. BS8 1TU, UK.
David H.D. Warren, Department of Computer Science, University of Bristol, UK. Working at: Partnership in Advanced Computing Technologies Science Research Foundation, 10 Priory Road, Bristol. BS8 1TU, UK.
pp. 212
John Reisner, Headquarters, Standard Systems Group Automated Communications Systems Directorate
Tom S. Wailes, Air Force Institute of Technology
pp. 222
Wen-jann Yang, Department of Electrical and Computer Engineering The State University of New York at Buffalo
Ramalingam Sridhar, Department of Electrical and Computer Engineering The State University of New York at Buffalo
Victor Demjanenko, Department of Electrical and Computer Engineering The State University of New York at Buffalo
pp. 232
Session IV-B: Caches
B. Calder, Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
D. Grunwald, Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
J. Emer, Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
pp. 244
Thomas Alexander, Departments of Computer Science and Electrical Engineering Duke University
Gershon Kedem, Departments of Computer Science and Electrical Engineering Duke University
pp. 254
Session V-A: High-Performance Processors
R. Espasa, Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
M. Valero, Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 281
Manu Gulati, NexGen Inc.
Nader Bagherzadeh, Electrical and Computer Engineering University of California, Irvine, CA 92714
pp. 291
Session V-B: Cache Protocols
Craig Anderson, Apple Computer
Anna R. Karlin, Department of Computer Science and Engineering University of Washington
pp. 303
Masafumi Takahashi, Research and Development Center, Toshiba Corporation
Hiroyuki Takano, Research and Development Center, Toshiba Corporation
Emi Kaneko, Research and Development Center, Toshiba Corporation
Seigo Suzuki, Research and Development Center, Toshiba Corporation
pp. 314
Alain Raynaud, Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
Zheng Zhang, Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
Josep Torrellas, Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
pp. 323
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