• H
  • HPCA
  • 1995
  • 1st IEEE Symposium on High-Performance Computer Architecture
Advanced Search 
1st IEEE Symposium on High-Performance Computer Architecture
Raleigh, North Carolina
January 22-January 25
ISBN: 0-8186-6445-2
Table of Contents
Session I-A Register Management
Session I-B: Interconnection Networks
Chunming Qiao, Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
R. Melhem, Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 34
A. Sivasubramaniam, Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
M. Singla, Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
U. Ramachandran, Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
H. Venkateswaran, Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 54
Session II-A: Latency Reduction Techniques
D. Citron, Inst. of Comput. Sci., Hebrew Univ., Jerusalem, Israel
L. Rudolph, Inst. of Comput. Sci., Hebrew Univ., Jerusalem, Israel
pp. 90
Session II-B: Routing in Mesh
R. Libeskind-Hadas, Dept. of Comput. Sci., Harvey Mudd Coll., Claremont, CA, USA
E. Brandt, Dept. of Comput. Sci., Harvey Mudd Coll., Claremont, CA, USA
pp. 102
J.H. Upadhyay, Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
V. Varavithya, Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
P. Mohapatra, Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 112
C.M. Cunningham, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D.R. Avresky, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 122
Session III-A: Cache Memory
O. Temam, PRiSM Lab., Versailles Univ., France
N. Drach, PRiSM Lab., Versailles Univ., France
pp. 154
Session III B: Modeling and Performance Evaluation
Y.M. Boura, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
C.R. Das, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 166
R. Treiber, IBM Almaden Res. Center, San Jose, CA, USA
J. Menon, IBM Almaden Res. Center, San Jose, CA, USA
pp. 186
Session IV-A: Synchronization and Scheduling
S. Fiske, Artificial Intelligence Lab., MIT, Cambridge, MA, USA
W.J Dally, Artificial Intelligence Lab., MIT, Cambridge, MA, USA
pp. 222
Session IV-B: Memory Management
K. Westerholz, Corp. Res. & Dev., Siemens AG, Munich, Germany
S. Honal, Corp. Res. & Dev., Siemens AG, Munich, Germany
J. Plankl, Corp. Res. & Dev., Siemens AG, Munich, Germany
C. Hafer, Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 234
Jesung Kim, Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Sang Lyul Min, Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Sanghoon Jeon, Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Byoungchu Ahn, Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Deog-Kyoon Jeong, Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Chong Sang Kim, Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
pp. 243
S.A. Mckee, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
W.A. Wulf, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 253
Session V-A: Cache Coherence
C. Anderson, Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
J.-L. Baer, Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 264
A. Saulsbury, Inst. of Comput. Sci., Kista, Sweden
T. Wilkinson, Inst. of Comput. Sci., Kista, Sweden
J. Carter, Inst. of Comput. Sci., Kista, Sweden
A. Landin, Inst. of Comput. Sci., Kista, Sweden
pp. 276
L.I. Kontothanassis, Dept. of Comput. Sci., Rochester Univ., NY, USA
M.L. Scott, Dept. of Comput. Sci., Rochester Univ., NY, USA
pp. 286
Session V-B: Multithreaded Architecture
R. Govindarajan, Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
S.S. Nemawarkar, Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
P. LeNir, Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
pp. 298
T. Kawano, Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan
S. Kusakabe, Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan
R.-I. Taniguchi, Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan
M. Amamiya, Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan
pp. 308
Yamin Li, Comput. Archit. Lab., Aizu Univ., Japan
Wanming Chu, Comput. Archit. Lab., Aizu Univ., Japan
pp. 318
Session VI-A: Special Purpose Architectures
Y. Hur, ECE Dept., Texas Univ., Austin, TX, USA
S.A. Szygenda, ECE Dept., Texas Univ., Austin, TX, USA
E. Scott Fehr, ECE Dept., Texas Univ., Austin, TX, USA
G.E. Ott, ECE Dept., Texas Univ., Austin, TX, USA
Sungho Kang, ECE Dept., Texas Univ., Austin, TX, USA
pp. 340
V. Garg, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
D.E. Schimmel, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 348
Session VI-B: Code Optimization
J. Torrellas, Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
Chun Xia, Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
R. Daigle, Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
pp. 360
L.K. John, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
V. Reddy, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
P.T. Hulina, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
L.D. Coraor, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 370
De-Lei Lee, Dept. of Comput. Sci., York Univ., Toronto, Ont., Canada
pp. 380
Invited Session II: Uniprocessor Architectures for High Performance: Organizer: Yale Patt, University of Michigan
Usage of this product signifies your acceptance of the Terms of Use.