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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (1995)
Raleigh, North Carolina
Jan. 22, 1995 to Jan. 25, 1995
ISBN: 0-8186-6445-2
TABLE OF CONTENTS
Referees (PDF)
pp. xi
Session I-A Register Management
Session I-B: Interconnection Networks
Chunming Qiao , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
R. Melhem , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 34
F. Cappello , Univ. de Paris-Sud, Orsay, France
C. Germain , Univ. de Paris-Sud, Orsay, France
pp. 44
M. Singla , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
A. Sivasubramaniam , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
H. Venkateswaran , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 54
Session II-A: Latency Reduction Techniques
D. Citron , Inst. of Comput. Sci., Hebrew Univ., Jerusalem, Israel
pp. 90
Session II-B: Routing in Mesh
R. Libeskind-Hadas , Dept. of Comput. Sci., Harvey Mudd Coll., Claremont, CA, USA
pp. 102
V. Varavithya , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
J.H. Upadhyay , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 112
C.M. Cunningham , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D.R. Avresky , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 122
Session III-A: Cache Memory
DASC cache (Abstract)
A. Seznec , IRISA, Rennes, France
pp. 134
O. Temam , PRiSM Lab., Versailles Univ., France
N. Drach , PRiSM Lab., Versailles Univ., France
pp. 154
Session III B: Modeling and Performance Evaluation
Y.M. Boura , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
C.R. Das , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 166
R. Treiber , IBM Almaden Res. Center, San Jose, CA, USA
pp. 186
Session IV-A: Synchronization and Scheduling
D.K. Panda , Dept. of Comput. & Inf. Sci., Ohio State Univ., Columbus, OH, USA
pp. 200
S. Fiske , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
pp. 222
Session IV-B: Memory Management
K. Westerholz , Corp. Res. & Dev., Siemens AG, Munich, Germany
S. Honal , Corp. Res. & Dev., Siemens AG, Munich, Germany
J. Plankl , Corp. Res. & Dev., Siemens AG, Munich, Germany
C. Hafer , Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 234
Sang Lyul Min , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Sanghoon Jeon , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Byoungchu Ahn , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Deog-Kyoon Jeong , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Jesung Kim , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
pp. 243
S.A. Mckee , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 253
Session V-A: Cache Coherence
C. Anderson , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 264
T. Wilkinson , Inst. of Comput. Sci., Kista, Sweden
J. Carter , Inst. of Comput. Sci., Kista, Sweden
A. Saulsbury , Inst. of Comput. Sci., Kista, Sweden
pp. 276
L.I. Kontothanassis , Dept. of Comput. Sci., Rochester Univ., NY, USA
pp. 286
Session V-B: Multithreaded Architecture
R. Govindarajan , Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
S.S. Nemawarkar , Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
P. LeNir , Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
pp. 298
S. Kusakabe , Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan
R.-I. Taniguchi , Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan
T. Kawano , Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan
pp. 308
Yamin Li , Comput. Archit. Lab., Aizu Univ., Japan
pp. 318
Session VI-A: Special Purpose Architectures
Y. Hur , ECE Dept., Texas Univ., Austin, TX, USA
S.A. Szygenda , ECE Dept., Texas Univ., Austin, TX, USA
E. Scott Fehr , ECE Dept., Texas Univ., Austin, TX, USA
G.E. Ott , ECE Dept., Texas Univ., Austin, TX, USA
Sungho Kang , ECE Dept., Texas Univ., Austin, TX, USA
pp. 340
V. Garg , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 348
Session VI-B: Code Optimization
J. Torrellas , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
Chun Xia , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
R. Daigle , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
pp. 360
V. Reddy , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
P.T. Hulina , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
L.D. Coraor , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 370
De-Lei Lee , Dept. of Comput. Sci., York Univ., Toronto, Ont., Canada
pp. 380
Invited Session II: Uniprocessor Architectures for High Performance: Organizer: Yale Patt, University of Michigan
Author Index (PDF)
pp. 393
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