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1st IEEE Symposium on High-Performance Computer Architecture
Access ordering and memory-conscious cache utilization
Raleigh, North Carolina
January 22-January 25
ISBN: 0-8186-6445-2
ASCII Text
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S.A. Mckee, W.A. Wulf, "Access ordering and memory-conscious cache utilization," High-Performance Computer Architecture, International Symposium on, pp. 253, 1st IEEE Symposium on High-Performance Computer Architecture, 1995.
 
 
BibTex
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@article{ 10.1109/HPCA.1995.386537,
author = {S.A. Mckee and W.A. Wulf},
title = {Access ordering and memory-conscious cache utilization},
journal ={High-Performance Computer Architecture, International Symposium on},
volume = {0},
year = {1995},
isbn = {0-8186-6445-2},
pages = {253},
doi = {http://doi.ieeecomputersociety.org/10.1109/HPCA.1995.386537},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - High-Performance Computer Architecture, International Symposium on
TI - Access ordering and memory-conscious cache utilization
SN - 0-8186-6445-2
SP
EP
A1 - S.A. Mckee,
A1 - W.A. Wulf,
PY - 1995
KW - cache storage; storage management; performance evaluation; memory-conscious cache utilization; memory bandwidth; access ordering; memory performance; analytic models; Intel i860XR; benchmark timings
VL - 0
JA - High-Performance Computer Architecture, International Symposium on
ER -
 
S.A. Mckee, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
W.A. Wulf, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
As processor speeds increase relative to memory speeds, memory bandwidth is rapidly becoming the limiting performance, factor for many applications. Several approaches to bridging this performance gap have been suggested. This paper examines one approach, access ordering, and pushes its limits to determine bounds on memory performance. We present several access-ordering schemes, and compare their performance, developing analytic models and partially validating these with benchmark timings on the Intel i860XR.
Index Terms:
cache storage; storage management; performance evaluation; memory-conscious cache utilization; memory bandwidth; access ordering; memory performance; analytic models; Intel i860XR; benchmark timings
Citation:
S.A. Mckee, W.A. Wulf, "Access ordering and memory-conscious cache utilization," hpca, pp.253, 1st IEEE Symposium on High-Performance Computer Architecture, 1995
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