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High Performance Interconnects, 2004. Proceedings. 12th Annual IEEE Symposium on
Stanford, CA, USA
August 05-August 07
ISBN: 0-7803-8686-8
Table of Contents
Keynote and Panels
Session 1: System Level Interconnects
Jiuxing Liu, Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
A. Mamidala, Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
A. Vishnu, Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
D.K. Panda, Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
pp. 13-19
D.K. Panda, Oak Ridge Nat. Lab., TN, USA
J.S. Vetter, Oak Ridge Nat. Lab., TN, USA
P.H. Worley, Oak Ridge Nat. Lab., TN, USA
pp. 20-25
Session 2: Packet Classification And Lookup
Fang Yu, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.H. Katz, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 28-34
Mei Wang, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
S. Deering, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
T. Hain, Oak Ridge Nat. Lab., TN, USA
L. Dunn, Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
pp. 35-40
M.J. Akhbarizadeh, Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA
M. Nourani, Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA
pp. 41-46
Session 3: Routers and Switches
S. Arekapudi, Comput. Syst. Lab., Stanford Univ., CA, USA
Shang-Tse Chuang, Comput. Syst. Lab., Stanford Univ., CA, USA
I. Keslassy, Oak Ridge Nat. Lab., TN, USA
N. McKeown, Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
pp. 48-53
G. Shrimali, Comput. Syst. Lab., Stanford Univ., CA, USA
I. Keslassy, Comput. Syst. Lab., Stanford Univ., CA, USA
N. McKeown, Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 54-60
P. Bhargava, Comput. Syst. Lab., Stanford Univ., CA, USA
S.C. Krishnan, Comput. Syst. Lab., Stanford Univ., CA, USA
R. Panigrahy, Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 61-67
Session 4: Security and Network Processors
N. Weaver, Comput. Syst. Lab., Stanford Univ., CA, USA
D. Ellis, Comput. Syst. Lab., Stanford Univ., CA, USA
S. Staniford, Comput. Syst. Lab., Stanford Univ., CA, USA
V. Paxson, Dept. of Comput. & Sci. & Eng., Ohio State Univ., Columbus, OH, USA
pp. 70-76
B. Madhusudan, Dept. of Comput. Sci. & Eng., Washington Univ., St. Louis, MO, USA
J. Lockwood, Dept. of Comput. Sci. & Eng., Washington Univ., St. Louis, MO, USA
pp. 77-83
R. Westrelin, Sun Microsystems, Inc., Santa Clara, CA, USA
N. Fugier, Sun Microsystems, Inc., Santa Clara, CA, USA
E. Nordmark, Sun Microsystems, Inc., Santa Clara, CA, USA
K. Kunze, Sun Microsystems, Inc., Santa Clara, CA, USA
E. Lemoine, Sun Microsystems, Inc., Santa Clara, CA, USA
pp. 84-90
Session 5: Architectures
A.K. Kodi, Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
A. Louri, Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 92-97
A. Raniwala, Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
Tzi-cker Chiueh, Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. 98-104
Copyright (Abstract)
pp. iv-iv
Patrons (Abstract)
pp. xi-xi
L. Valcarenghi, Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. 105-106
G. Manimaran, Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 109-108
Author Index (Abstract)
pp. 111-111
J.B. Lyles, Nortel Networks
A. Watters, Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. vii-vii
J. Sterbenz, University of Massachusetts
D. Stiliadis, Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. viii-viii
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