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11 th Symposium on High Performance Interconnects
A Wave-Pipelined On-chip Interconnect Structure for Networks-on-Chips
Stanford, California
August 20-August 22
ISBN: 0-7695-2012-x
Jiang Xu, Princeton University
Wayne Wolf, Princeton University
The paper describes a structured communication link design technique, wave-pipelined interconnect, for networks-on-chip. We achieved 3.45GHz and 55.2Gbps throughput on a 10mm 16bit interconnection in a 0.25um technology. It uses 0.079mm2 of area, and it only needs 18.8pJ to transmit one bit. We reduce 79% crosstalk delay by using two techniques -- interleaved lines and misaligned repeaters. This paper shows the various techniques we used to save power and area and achieve high performance in a relative old technology in detail. Wave-pipelined interconnect design is relatively easy, but many features of it give a large and flexible design space for high-performance chips.
Citation:
Jiang Xu, Wayne Wolf, "A Wave-Pipelined On-chip Interconnect Structure for Networks-on-Chips," hoti, pp.10, 11 th Symposium on High Performance Interconnects, 2003
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