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2007 IEEE International High Level Design Validation and Test Workshop
Irvine, CA, USA
November 07-November 09
ISBN: 978-1-4244-1480-2
Table of Contents
Papers
Mohammad Hosseinabady, University of Bristol, UK
Mohammad Reza Kakoee, University of Tehran, Iran
Jimson Mathew, University of Bristol, UK
Dhiraj K. Pradhan, University of Bristol, UK
pp. 3-10
Eric Cheung, Department of Computer Science and Engineering, University of California Riverside, Riverside, 92521, USA
Harry Hsieh, Department of Computer Science and Engineering, University of California Riverside, Riverside, 92521, USA
Felice Balarin, Cadence Design Systems, Berkeley, California 95134, USA
pp. 21-28
Lucky Lo Chi Yu Lo, Center for Embedded Computer Systems, UC Irvine, CA 92697, USA
Samar Abdi, Center for Embedded Computer Systems, UC Irvine, CA 92697, USA
pp. 29-36
Eric Cheung, Department of Computer Science and Engineering, University of California Riverside, Riverside, 92521, USA
Harry Hsieh, Department of Computer Science and Engineering, University of California Riverside, Riverside, 92521, USA
Felice Balarin, Cadence Design Systems, Berkeley, California 95134, USA
pp. 37-44
Jai Kumar, Sun Microsystems, Microelectronics Group, 4210 Network Circle, MS USCA21-114, Santa Clara, CA 95054, USA
Catherine Ahlschlager, Sun Microsystems, Microelectronics Group, 4210 Network Circle, MS USCA21-114, Santa Clara, CA 95054, USA
Peter Isberg, Sun Microsystems, Microelectronics Group, 4210 Network Circle, MS USCA21-114, Santa Clara, CA 95054, USA
pp. 47
Intel (Abstract)
Bojan Tommy, Intel Corporation, Intel Development Center, M.T.M. Scientific Industries Center, Haifa 31015, Israel
Frumkin Igor, Intel Corporation, Intel Development Center, M.T.M. Scientific Industries Center, Haifa 31015, Israel
Mauri Robert, Intel Corporation, 2088 Center Drive, MS 301, DuPont, WA 98327, USA
pp. 53-56
Tao Lv, Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
Tong Xu, Microprocessor Center, Dept. of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
Yang Zhao, Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
Huawei Li, Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
Xiaowei Li, Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
pp. 59-64
Kai-hui Chang, EECS Department, University of Michigan, 48109-2121, USA
Ilya Wagner, EECS Department, University of Michigan, 48109-2121, USA
Valeria Bertacco, EECS Department, University of Michigan, 48109-2121, USA
Igor L. Markov, EECS Department, University of Michigan, 48109-2121, USA
pp. 65-72
Eric Cheung, University of California, 92521, USA
Xi Chen, Novas Software, Inc. San Jose, California 95110, USA
Furshing Tsai, Novas Software, Inc. San Jose, California 95110, USA
Yu-Chin Hsu, Novas Software, Inc. San Jose, California 95110, USA
Harry Hsieh, University of California, 92521, USA
pp. 73-80
Deepak A. Mathaikutty, CESCA, Virginia Tech, Blacksburg, VA 24061, USA
Sumit Ahuja, CESCA, Virginia Tech, Blacksburg, VA 24061, USA
Ajit Dingankar, Validation Technology, Intel Corporation, Folsom, CA 95630, USA
Sandeep Shukla, CESCA, Virginia Tech, Blacksburg, VA 24061, USA
pp. 83-90
Mingsong Chen, Computer and Information Science and Engineering University of Florida, Gainesville, FL 32611, USA
Prabhat Mishra, Computer and Information Science and Engineering University of Florida, Gainesville, FL 32611, USA
Dhrubajyoti Kalita, Intel Corporation 1900 Prairie City Road, Folsom, CA 95630, USA
pp. 91-96
Bijan Alizadeh, VLSI Design and Education Center (VDEC), University of Tokyo, Japan
Masahiro Fujita, VLSI Design and Education Center (VDEC), University of Tokyo, Japan
pp. 97-104
Xiaofang Chen, Ganesh Gopalakrishnan School of Computing, University of Utah Salt Lake City, 84112, USA
Yu Yang, Ganesh Gopalakrishnan School of Computing, University of Utah Salt Lake City, 84112, USA
Michael Delisi, Ganesh Gopalakrishnan School of Computing, University of Utah Salt Lake City, 84112, USA
Ching-Tsun Chou, Intel Corporation Santa Clara, CA 95054, USA
pp. 107-114
Joseph Buck, Synopsys Inc. Advanced Technology Group, Japan
Dong Wang, Synopsys Inc. Advanced Technology Group, Japan
Yunshan Zhu, Independent Consultant, Japan
pp. 115-122
Noureddine Chabini, Department of Electrical and Computer Engineering, Royal Military College of Canada, USA
Wayne Wolf, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA
pp. 123-130
Peter A. Milder, Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, U.S.A.
Franz Franchetti, Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, U.S.A.
James C. Hoe, Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, U.S.A.
Markus Puschel, Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, U.S.A.
pp. 137-139
Krste Asanovic, Computer Science Division, University of California at Berkeley, USA
pp. 140-142
Tommy Bojan, Intel Corporation, Intel Development Center, M.T.M, Scientific Industries Center, Haifa 31015, Israel
Manuel Aguilar Arreola, Intel Corporation, Latin America Design Services, Israel
pp. 145-150
Onur Guzey, Department of ECE, UC-Santa Barbara, USA
Li-C. Wang, Department of ECE, UC-Santa Barbara, USA
pp. 151-158
Shireesh Verma, Center for Embedded Computer Systems, Department of Computer Science, University of California, Irvine, CA 92697, USA
Ian G. Harris, Center for Embedded Computer Systems, Department of Computer Science, University of California, Irvine, CA 92697, USA
Kiran Ramineni, Center for Embedded Computer Systems, Department of Computer Science, University of California, Irvine, CA 92697, USA
pp. 159-164
A. Benso, Politecnico di Torino, Dipartimento di Automatica e Informatica, Italy
S. Di Carlo, Politecnico di Torino, Dipartimento di Automatica e Informatica, Italy
P. Prinetto, Politecnico di Torino, Dipartimento di Automatica e Informatica, Italy
A. Bosio, Laboratoire d
pp. 171-178
Marco Murciano, Dipartimento di Automatica ed Informatica, Politecnico di Torino, Torino, Italy
Massimo Violante, Dipartimento di Automatica ed Informatica, Politecnico di Torino, Torino, Italy
pp. 179-186
F. Fummi, University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy
G. Perbellini, University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy
D. Quaglia, University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy
S. Vinco, University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy
pp. 187-194
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