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Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (2004)
Sonoma Valley, CA, USA
Nov. 10, 2004 to Nov. 12, 2004
ISBN: 0-7803-8714-7
TABLE OF CONTENTS
Committees (PDF)
pp. iv
Session 1: Formal Techniques
Chia-Chih Yen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jing-Yang Jou , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 3-8
W.N.N. Hung , Synplicity Inc., Sunnyvale, CA, USA
N. Narasimhan , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 9-13
Table of contents (Abstract)
pp. v-viii
P.M. Peranandam , Dept. of Comput. Eng., Tubingen Univ., Germany
R.J. Weiss , Dept. of Comput. Eng., Tubingen Univ., Germany
J. Ruf , Dept. of Comput. Eng., Tubingen Univ., Germany
T. Kropf , Dept. of Comput. Eng., Tubingen Univ., Germany
W. Rosenstiel , Dept. of Comput. Eng., Tubingen Univ., Germany
pp. 15-18
A. Habibi , Concordia Univ., Montreal, Que., Canada
S. Tahar , Concordia Univ., Montreal, Que., Canada
pp. 19-22
Session 2: Processor-oriented Validation
S. Shamshiri , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
H. Esmaeilzadeh , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
Z. Navabi , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
pp. 25-29
J.T. Higgins , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
M.D. Aagaard , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
pp. 31-36
I. Bayraktaroglu , Design for Test Technol. Group, Sun MicroSystems Inc., Sunnyvale, CA, USA
M. d'Abreu , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
pp. 37-40
M.N. Velev , Design for Test Technol. Group, Sun MicroSystems Inc., Sunnyvale, CA, USA
pp. 41-46
Session 3: Decision Diagrams for Verification
T. Feng , Cadence Design Syst. Inc., San Jose, CA, USA
L.-C. Wang , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
K.-T. Cheng , Electr. & Comput. Eng. Dept., Tehran Univ., Iran
A.C.-C. Lin , Dept. of Comput. Eng., Tubingen Univ., Germany
pp. 49-54
D. Gomez-Prado , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Q. Ren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
S. Askar , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
M. Ciesielski , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
E. Boutillon , Dept. of Comput. Eng., Tubingen Univ., Germany
pp. 55-59
T.L. Rajaprabhu , Bristol Univ., UK
A.K. Singh , Bristol Univ., UK
A.M. Jabir , Bristol Univ., UK
D.K. Pradhan , Bristol Univ., UK
pp. 61-66
Session 4: Validation Pattern Generation
F. Fummi , Dipt. di Informatica, Univ. di Verona, Italy
C. Marconcini , Dipt. di Informatica, Univ. di Verona, Italy
G. Pravadelli , Dipt. di Informatica, Univ. di Verona, Italy
pp. 69-74
M. Braun , STZ Softwaretechnik, Esslingen, Germany
S. Fine , Dipt. di Informatica, Univ. di Verona, Italy
A. Ziv , Dipt. di Informatica, Univ. di Verona, Italy
pp. 75-80
J. Campos , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
H. Al-Asaad , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
pp. 81-86
Session 5: Behavioral Modeling
Syed Suhaib , FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Deepak Mathaikutty , FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Sandeep Shukla , FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 89-94
T. Margaria , Gottingen Univ., Germany
O. Niese , FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
H. Raffelt , FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
B. Steffen , Bristol Univ., UK
pp. 95-100
Copyright (Abstract)
pp. ii
Commiftees (Abstract)
pp. iv
S. Abdi , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
D. Gajski , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 101-106
Session 6: Fault Coverage Analysis
A. AI- Yamani , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 109-114
Yuan-Bin Sha , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
Mu-Shun Lee , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
Mu-Shun Lee , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
pp. 115-120
X. Liu , Texas Instrum. Inc., Dallas, TX, USA
M.S. Hsiao , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
pp. 121-126
Session 7: SAT Solving Approaches
Rajat Arora , Cadence Design Syst. Inc., San Jose, CA, USA
M.S. Hsiao , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
pp. 129-134
V. Durairaj , Dept. of Electr. & Comput; Eng., Utah Univ., Salt Lake City, UT, USA
P. Kalla , Dept. of Electr. & Comput; Eng., Utah Univ., Salt Lake City, UT, USA
pp. 135-140
V. Duraira , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
P. Kalla , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
pp. 141-146
Session 8: Validation of Network Architectures
C. Ciordas , Eindhoven Univ. of Technol., Netherlands
T. Basten , Eindhoven Univ. of Technol., Netherlands
A. Radulescu , Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
K. Goossens , Bristol Univ., UK
J. Meerbergen , Dept. of Comput. Eng., Tubingen Univ., Germany
pp. 149-154
J. Yu , California Univ., Riverside, CA, USA
W. Wu , California Univ., Riverside, CA, USA
X. Chen , California Univ., Riverside, CA, USA
H. Hsieh , California Univ., Riverside, CA, USA
J. Yang , California Univ., Riverside, CA, USA
pp. 155-160
F. Corno , Dip. Automatica e Informatica, Politecnico di Torino, Italy
J. Perez , California Univ., Riverside, CA, USA
M. Ramasso , California Univ., Riverside, CA, USA
M. Reorda , California Univ., Riverside, CA, USA
M. Violante , California Univ., Riverside, CA, USA
pp. 161-164
Session 9: High-level Validation
P.K. Murthy , Fujitsu Labs. of America, Sunnyvale, CA, USA
S.R. Rajan , California Univ., Riverside, CA, USA
K. Takayama , California Univ., Riverside, CA, USA
pp. 167-172
D. Gil , Fault Tolerant Syst. Group, Polytech. Univ. of Valencia, Spain
J. Gracia , Fault Tolerant Syst. Group, Polytech. Univ. of Valencia, Spain
J.C. Baraza , Fault Tolerant Syst. Group, Polytech. Univ. of Valencia, Spain
P.J. Gil , Fault Tolerant Syst. Group, Polytech. Univ. of Valencia, Spain
pp. 173-178
M. Fujita , VLSI Design & Educ. Center, Tokyo Univ., Japan
pp. 179-184
Session 10: Panel - "Driving the Intelligent Testbench: Are we there yet?"
H.D. Foster , VLSI Design & Educ. Center, Tokyo Univ., Japan
pp. 188
G. Smith , VLSI Design & Educ. Center, Tokyo Univ., Japan
pp. 189
Author Index (Abstract)
pp. 191
Back cover (Abstract)
pp. 194
A.J. Hu , VLSI Design & Educ. Center, Tokyo Univ., Japan
I.G. Harris , Fault Tolerant Syst. Group, Polytech. Univ. of Valencia, Spain
pp. iii
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