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Proceedings Sixth IEEE International High-Level Design Validation and Test Workshop (2001)
Monterey, CA, USA
Nov. 9, 2001 to Nov. 9, 2001
ISBN: 0-7695-1411-1
TABLE OF CONTENTS
Session 1: Design Validation of Microprocessors
Prabhat Mishra , University of California, Irvine
Nikil Dutt , University of California, Irvine
Alex Nicolau , University of California, Irvine
pp. 9
Session 2: Techniques for High Level Design Validation and Test
Session 3: Invited Session: State-of-the-Art Formal Verification Techniques
Hans Eveking , Darmstadt University of Technology
Jens Levihn , Darmstadt University of Technology
Gerd Ritter , Darmstadt University of Technology
pp. 45
Session 4: Short Papers: High Level Verification and Analysis
Sandeep K. Shukla , University of California at Irvine
Rajesh K. Gupta , University of California at Irvine
pp. 53
Byeong Min , Texas A&M University
Gwan Choi , Texas A&M University
pp. 58
P. Kalla , University of Massachusetts
M. Ciesielski , University of Massachusetts
B. Rouzeyre , LIRMM
pp. 70
Session 5: Short papers: High Level Timing Verification and Testing
Sungjoo Yoo , SLS group, TIMA/INPG
Lovic Gauthier , SLS group, TIMA/INPG
Ahmed A. Jerraya , SLS group, TIMA/INPG
pp. 79
Fei Xin , University of Massachusetts
Srikanth Arekapudi , University of Massachusetts
Ian G. Harris , University of Massachusetts
pp. 83
Kai Richter , Technical University of Braunschweig
Marek Jersak , Technical University of Braunschweig
pp. 89
Session 6: Verification of Real Life Designs
Kai S. Juse , Technical University of Darmstadt
Anne Condon , Univ. of British Columbia
Alan J. Hu , Univ. of British Columbia
Marius Laza , Univ. of British Columbia
Michael Leslie , Univ. of British Columbia
Tim Braun , Technical University of Darmstadt
pp. 103
Roope Kaivola , Intel Corporation
Naren Narasimhan , Intel Corporation
pp. 115
Session 7: High-Level Specification and Verification
Felice Balarin , Cadence Berkeley Laboratories
Jerry Burch , Cadence Berkeley Laboratories
Luciano Lavagno , Cadence Berkeley Laboratories
Yosinori Watanabe , Cadence Berkeley Laboratories
Roberto Passerone , University of California at Berkeley
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
pp. 129
Session 8: High-Level Test Generation and Coverage Analysis
Ian G. Harris , University of Massachusetts
pp. 151
Farzan Fallah , Fujitsu Laboratories of America, Inc.
pp. 157
Session 9: Improved Techniques for Boolean Reasoning
Dong Wang , Carnegie Mellon University
Edmund Clarke , Carnegie Mellon University
Yunshan Zhu , Synopsys Inc.
James Kukula , Synopsys Inc.
pp. 165
John Moondanos , Intel Architecture Group
Daher Kaiss , Intel Architecture Group
Zurab Khasidashvili , Intel Architecture Group
pp. 171
Kwang-Ting Cheng , Univ. of California, Santa Barbara
Chung-Yang Huang , Verplex Systems Inc
pp. 177
Author Index (PDF)
pp. 183
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