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Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Constraints Specification at Higher Levels of Abstraction
Monterey, California
December 07-December 09
ISBN: 0-7695-1411-1
ASCII Text
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Felice Balarin, Jerry Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto Sangiovanni-Vincentelli, "Constraints Specification at Higher Levels of Abstraction," 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT), pp. 129, Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01), 2001.
 
 
BibTex
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@article{ 10.1109/HLDVT.2001.972819,
author = {Felice Balarin and Jerry Burch and Luciano Lavagno and Yosinori Watanabe and Roberto Passerone and Alberto Sangiovanni-Vincentelli},
title = {Constraints Specification at Higher Levels of Abstraction},
journal ={2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)},
volume = {0},
year = {2001},
isbn = {0-7695-1411-1},
pages = {129},
doi = {http://doi.ieeecomputersociety.org/10.1109/HLDVT.2001.972819},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)
TI - Constraints Specification at Higher Levels of Abstraction
SN - 0-7695-1411-1
SP
EP
A1 - Felice Balarin,
A1 - Jerry Burch,
A1 - Luciano Lavagno,
A1 - Yosinori Watanabe,
A1 - Roberto Passerone,
A1 - Alberto Sangiovanni-Vincentelli,
PY - 2001
VL - 0
JA - 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)
ER -
 
Felice Balarin, Cadence Berkeley Laboratories
Jerry Burch, Cadence Berkeley Laboratories
Luciano Lavagno, Cadence Berkeley Laboratories
Yosinori Watanabe, Cadence Berkeley Laboratories
Roberto Passerone, University of California at Berkeley
Alberto Sangiovanni-Vincentelli, University of California at Berkeley
We are proposing a formalism to express performance constraints at a high level of abstraction. The formalism allows specifying design performance constraints even before all low level details necessary to evaluate them are known. It is based on a solid mathematical foundation, to remove any ambiguity in its interpretation, and yet it allows quite simple and natural specification of many typical constraints.Once the design details are known, the satisfaction of constraints can be checked either by simulation, or by formal techniques like theorem proving, and, in some cases, by automatic model checking.
Citation:
Felice Balarin, Jerry Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto Sangiovanni-Vincentelli, "Constraints Specification at Higher Levels of Abstraction," hldvt, pp.129, Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01), 2001
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