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Fifth IEEE International High-Level Design Validation and Test Workshop (HLDVT'00)
Berkeley, California
November 08-November 10
ISBN: 0-7695-0786-7
Table of Contents
Session 1: Advances in High-Level Test I: Chair: Kapila Udawatta, Intel
F. Corno, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
G. Cumani, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
G. Squillero, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 3
V.M. Vedula, Center for Comput. Eng. Res., Texas Univ., Austin, TX, USA
J.A. Abraham, Center for Comput. Eng. Res., Texas Univ., Austin, TX, USA
pp. 9
C. Paoli, CNRS, Corsica Univ., Corte, France
M.L. Nivet, CNRS, Corsica Univ., Corte, France
J.F. Santucci, CNRS, Corsica Univ., Corte, France
pp. 15
M. Lajolo, NEC USA C&C Res. Lab., USA
M. Rebaudengo, NEC USA C&C Res. Lab., USA
M.S. Reorda, NEC USA C&C Res. Lab., USA
M. Violante, NEC USA C&C Res. Lab., USA
L. Lavagno, NEC USA C&C Res. Lab., USA
pp. 21
Session 2: Validation and Test for Microprocessor Designs: Chair: Magdy Abadir, Motorola
M. Beardo, Politecnico di Milano, Italy
F. Bruschi, Politecnico di Milano, Italy
F. Ferrandi, Politecnico di Milano, Italy
D. Sciuto, Politecnico di Milano, Italy
pp. 29
M. Pflanz, CE Res. Group, Tech. Univ. Cottbus, Germany
C. Galke, CE Res. Group, Tech. Univ. Cottbus, Germany
H.T. Vierhaus, CE Res. Group, Tech. Univ. Cottbus, Germany
pp. 34
H. Tomiyama, Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
T. Yoshino, Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
N. Dutt, Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 40
Session 3: Hardware/Software Co-Validation: Chair: Abhijit Ghosh, Synopsys
B. Vermeulen, Philips Res. Lab., Eindhoven, Netherlands
G.J. van Rootselaar, Philips Res. Lab., Eindhoven, Netherlands
pp. 47
D. Panigrahi, Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
C.N. Taylor, Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
S. Dey, Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 53
K.A. Tomko, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
A. Tiwari, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
pp. 59
Session 4: Formal Verification Techniques and Applications: Chair: Masahiro Fujita, University of Tokyo
M.S. Jahanpour, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
E. Cerny, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
pp. 71
Session 5: Issues in High-Level Design Validation: Chair: Timothy Kam
A. Hajjar, Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
T. Chen, Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
A. von Mayrhauser, Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
pp. 89
H. Yamashita, Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
H. Yasnura, Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
F.N. Eko, Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
Cao Yun, Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
pp. 95
Session 6:Advances in High-Level Test II: Chair: Irith Pomeranz, Purdue University
S. Seshadri, Mentor Graphics Corp., Warren, NJ, USA
M.S. Hsiao, Mentor Graphics Corp., Warren, NJ, USA
pp. 105
Tianjing Jiang, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
R.H. Klenke, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
J.H. Aylor, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
Gang Han, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
pp. 112
A. von Mayhauser, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
T. Chen, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
J. Kok, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
C. Anderson, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
A. Read, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
A. Haijar, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
pp. 124
Session 7: Formal Verification Techniques: Chair: Tom Henzinger, UC Berkeley
Yee-Wing Hsieh, Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
S.P. Levitan, Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
pp. 133
H. Hsieh, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
F. Balarin, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 139
M. Jones, Sch. of Comput., Utah Univ., Salt Lake City, UT, USA
G. Gopalakrishnan, Sch. of Comput., Utah Univ., Salt Lake City, UT, USA
pp. 147
Session 8: Advances in Simulation-Based Verification: Chair: Alan Hu, University of British Columbia
F. Wolf, Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
R. Ernst, Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
pp. 155
J. Ruf, Wilhelm-Schickard-Inst. fur Inf., Tubingen Univ., Germany
D.W. Hoffmann, Wilhelm-Schickard-Inst. fur Inf., Tubingen Univ., Germany
T. Kropf, Wilhelm-Schickard-Inst. fur Inf., Tubingen Univ., Germany
W. Rosenstiel, Wilhelm-Schickard-Inst. fur Inf., Tubingen Univ., Germany
pp. 161
M.T. Lazarescu, Cadence Design Syst. Inc., San Jose, CA, USA
J.R. Bammi, Cadence Design Syst. Inc., San Jose, CA, USA
E. Harcourt, Cadence Design Syst. Inc., San Jose, CA, USA
L. Lavagno, Cadence Design Syst. Inc., San Jose, CA, USA
M. Lajolo, Cadence Design Syst. Inc., San Jose, CA, USA
pp. 167
C. Hansen, Forschungszentrum Inf., Karlsruhe Univ., Germany
W. Rosenstiel, Forschungszentrum Inf., Karlsruhe Univ., Germany
pp. 173
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