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36th Annual Hawaii International Conference on System Sciences (HICSS'03) - Track 9
Big Island, Hawaii
January 06-January 09
ISBN: 0-7695-1874-5
Dominique Borrione, TIMA Laboratory
Menouer Boubekeur, TIMA Laboratory
Emil Dumitrescu, TIMA Laboratory
Marc Renaudin, TIMA Laboratory
Jean-Baptiste Rigaud, TIMA Laboratory
Antoine Sirianni, TIMA Laboratory
This paper discusses the integration of model-checking inside a design flow for Quasi-Delay Insensitive circuits. Both the formal validation of an asynchronous behavioral specification and the formal verification of the asynchronous synthesis result are considered. The method follows several steps: formal model extraction, model simplification, environment modeling, writing temporal properties and proof. The approach is illustrated on a small, yet characteristic, asynchronous selection circuit.
Citation:
Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Sirianni, "An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow," hicss, vol. 9, pp.279b, 36th Annual Hawaii International Conference on System Sciences (HICSS'03) - Track 9, 2003
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