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Big Island, HI, USA
Jan. 6, 2003 to Jan. 9, 2003
ISBN: 0-7695-1874-5
pp: 279a
Satoshi Komatsu , University of Tokyo
Hiroshi Saito , University of Tokyo
Kenshu Seto , University of Tokyo
Masahiro Fujita , University of Tokyo
Yoshihisa Kojima , University of Tokyo
In the age of highly integrated system LSIs, design methodologies for shorter time-to-market and higher re-programmability after the chip fabrications are now key re-search issues because of the difficulty of complete verifica-tion before tape-out of LSI designs. In this paper, we first introduce a IP-based VLSI architecture that consists of a main processor and an additional hardware (both custom hard macros and FPGA on a single chip) specialized to be in charge of the specific instructions. We further replace the controller circuits of the specialized hardware with compact micro-controllers and memories by using IP libraries (hard macros), which results in the increase of the debuggability and the flexibility of design even for computations realized by hard macros. We call the proposed architecture as Field Modifiable Architecture (FMA). Experimental results confirm that our architecture can achieve significant performance improvement in terms of execution cycles and that EC (Engineering Change) can be successfully accommodated "after" chip fabrications.
Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Masahiro Fujita, Yoshihisa Kojima, "Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies", HICSS, 2003, 36th Hawaii International Conference on Systems Sciences, 36th Hawaii International Conference on Systems Sciences 2003, pp. 279a, doi:10.1109/HICSS.2003.1174810
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