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29th Hawaii International Conference on System Sciences (HICSS'96) Volume 1: Software Technology and Architecture
Maui, Hawaii
January 03-January 06
ISBN: 0-8186-7324-9
| ASCII Text | x | ||
| U. Wever, Q. Zheng, "Parallel Transient Analysis for Circuit Simulation," 2013 46th Hawaii International Conference on System Sciences, pp. 442, 29th Hawaii International Conference on System Sciences (HICSS'96) Volume 1: Software Technology and Architecture, 1996. | |||
| BibTex | x | ||
| @article{ 10.1109/HICSS.1996.495492, author = {U. Wever and Q. Zheng}, title = {Parallel Transient Analysis for Circuit Simulation}, journal ={2013 46th Hawaii International Conference on System Sciences}, volume = {0}, year = {1996}, issn = {1060-3425}, pages = {442}, doi = {http://doi.ieeecomputersociety.org/10.1109/HICSS.1996.495492}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2013 46th Hawaii International Conference on System Sciences TI - Parallel Transient Analysis for Circuit Simulation SN - 1060-3425 SP EP A1 - U. Wever, A1 - Q. Zheng, PY - 1996 VL - 0 JA - 2013 46th Hawaii International Conference on System Sciences ER - | |||
In this paper we discuss the application of domain decomposition methods to circuit simulation. This coarse grain parallelization guarantees low communication and thus achieves good speedup results on a workstation cluster. Especially with multi level Newton methods and iteration latency techniques, the communication can be reduced to a minimum. The application of these techniques make our parallel implementation very well suited for a workstation cluster with low communication performance.
Citation:
U. Wever, Q. Zheng, "Parallel Transient Analysis for Circuit Simulation," hicss, pp.442, 29th Hawaii International Conference on System Sciences (HICSS'96) Volume 1: Software Technology and Architecture, 1996
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