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Ninth Great Lakes Symposium on VLSI
On Optimizing Test Strategies for Analog Cells
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
| ASCII Text | x | ||
| Anna M. Brosa, Joan Figueras, "On Optimizing Test Strategies for Analog Cells," Great Lakes Symposium on VLSI, pp. 92, Ninth Great Lakes Symposium on VLSI, 1999. | |||
| BibTex | x | ||
| @article{ 10.1109/GLSV.1999.757384, author = {Anna M. Brosa and Joan Figueras}, title = {On Optimizing Test Strategies for Analog Cells}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1999}, issn = {1066-1395}, pages = {92}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757384}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Great Lakes Symposium on VLSI TI - On Optimizing Test Strategies for Analog Cells SN - 1066-1395 SP EP A1 - Anna M. Brosa, A1 - Joan Figueras, PY - 1999 VL - 0 JA - Great Lakes Symposium on VLSI ER - | |||
The purpose of this paper is to analyze an optimization method to improve the testability of structural defects, such as bridges and opens, in low-power low-voltage analog circuits. The approach consists of finding an optimum subset of tests which maximizes the fault coverage with minimum cost. An application example is given to illustrate the proposal by studying the fault coverage obtained using different test sets on a simple 2-stage Nested Transconductance Capacitance Compensated (NGCC) amplifier.
Citation:
Anna M. Brosa, Joan Figueras, "On Optimizing Test Strategies for Analog Cells," glsvlsi, pp.92, Ninth Great Lakes Symposium on VLSI, 1999
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