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6th Great Lakes Symposium on VLSI
Ames, IA
March 22-March 23
ISBN: 0-8186-7502-0
Table of Contents
Session 1A: High-level Synthesis and Special Purpose Architecture I
Yun-Nan Chang, Department of Electrical Engineering University of Minnesota
Ching-Yi Wang, Department of Electrical Engineering University of Minnesota
Keshab K. Parhi, Department of Electrical Engineering University of Minnesota
pp. 0002
Jian-Feng Shi, Dept. of Electrical and Computer Engineering Iowa State University
Liang-Fang Chao, Dept. of Electrical and Computer Engineering Iowa State University
pp. 0014
Session 1B: Circuit Design and FPGA Architecture II
N.K. Ratha, Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
A.K. Jain, Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
D.T. Rover, Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
pp. 0029
Pong P. Chu, Dept Electrical Engineering Celeveland State University
pp. 0035
Session 2A: Physical Design I
Moazzem Hossain, Compass Design Automation San Jose, CA 95131
Bala Thumma, Compass Design Automation San Jose, CA 95131
Sunil Ashtaputre, Compass Design Automation San Jose, CA 95131
pp. 0044
Dirk Stroobandt, University of Ghent, Department of Electronics and Information Systems
Herwig van Marck, University of Ghent, Department of Electronics and Information Systems
Jan van Campenhout, University of Ghent, Department of Electronics and Information Systems
pp. 0050
Session 2B: High-level Synthesis and Special Purpose Architecture II
Session 3A: Physical Design II
James Loy, United States Military Academy, West Point, NY10996
Atul Garg, United States Military Academy, West Point, NY10996
Mukkai Krishnamoorthy, United States Military Academy, West Point, NY10996
John McDonald, United States Military Academy, West Point, NY10996
pp. 0096
Session 3B: Synthesis and Verification I
S. Tahar, University of Montreal
Z. Zhou, University of Montreal
X. Song, University of Montreal
E. Cerny, University of Montreal
Michel Langevin, GMD-SET, Shloss Birlinghoven, 53757 St. Augustin, Germany
pp. 0106
Chien-Chung Tsai, University of California, Santa Barbara, CA 93106
Malgorzata Marek-Sadowska, University of California, Santa Barbara, CA 93106
pp. 0118
L. Litan, University of Halle, Germany
P. Molitor, University of Halle, Germany
D. Möller, University of Halle, Germany
pp. 0126
Session 4A: Special Session on Issues in Performance Driven Layout
Manjit Borah, The Pennsylvania State University
Robert Michael Owens, The Pennsylvania State University
Mary Jane Irwin, The Pennsylvania State University
pp. 0137
John Lillis, University of California, San Diego
Chung-Kuan Cheng, University of California, San Diego
Ting-Ting Y. Lin, University of California, San Diego
pp. 0148
Guangqiu Chen, Department of Electronics and Communication Kyoto University
Hidetoshi Onodera, Department of Electronics and Communication Kyoto University
Keikichi Tamaru, Department of Electronics and Communication Kyoto University
pp. 0154
Session 4B: Low Power Design
Huzefa Mehta, Department of Computer Science and Engineering University Park, PA 16802
Robert Michael Owens, Department of Computer Science and Engineering University Park, PA 16802
Mary Jane Irwin, Department of Computer Science and Engineering University Park, PA 16802
pp. 0178
Session 5A: Physical Design III
Bradley S. Carlson, Dept. of EEDept. of ECE SUNY at Stony Brook Syracuse University
C.Y. Roger Chen, Dept. of EEDept. of ECE SUNY at Stony Brook Syracuse University
Dikran Meliksetian, Dept. of EEDept. of ECE SUNY at Stony Brook Syracuse University
pp. 0194
Session 5B: Testing I
Session 6A: High-level Synthesis and Special Purpose Architecture III
H. Djahanshahi, University of Windsor
M. Ahmadi, University of Windsor
G.A. Jullien, University of Windsor
W.C. Miller, University of Windsor
pp. 0228
C. Chantrapornchai, Dept. of Computer Science and Engineering Notre Dame, IN 46556
S. Tongsima, Dept. of Computer Science and Engineering Notre Dame, IN 46556
E. Sha, Dept. of Computer Science and Engineering Notre Dame, IN 46556
pp. 0234
Session 6B: Circuit Design II
Jose G. Delgado-Frias, State University of New York
Jabulani Nyathi, State University of New York
Chester L. Miller, State University of New York
Douglas H. Summerville, State University of New York
pp. 0246
Session 7A: Synthesis and Verification II
Shi-Yu Huang, University of California, Santa Barbara, CA
Kwang-Ting Cheng, University of California, Santa Barbara, CA
Kuang-Chien Chen, Fujitsu Laboratories of America
pp. 0277
Session 7B: Testing II
Irith Pomeranz, Electrical and Computer Engineering Department University of Iowa
Sudhakar M. Reddy, Electrical and Computer Engineering Department University of Iowa
Janak H. Patel, Center for Reliable & High-Performance Computing University of Illinois
pp. 0282
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