Transistor Chaining in CMOS Leaf Cells of Planar Topology

Bradley S. Carlson; C.Y. Roger Chen; Dikran Meliksetian

doi:10.1109/GLSV.1996.497619

G
GLSVLSI
1996
6th Great Lakes Symposium on VLSI
Abstract - Transistor Chaining in CMOS Leaf Cells of Planar Topology

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6th Great Lakes Symposium on VLSI

Transistor Chaining in CMOS Leaf Cells of Planar Topology

Ames, IA

March 22-March 23

ISBN: 0-8186-7502-0

	ASCII Text	x
	Bradley S. Carlson, C.Y. Roger Chen, Dikran Meliksetian, "Transistor Chaining in CMOS Leaf Cells of Planar Topology," Great Lakes Symposium on VLSI, pp. 0194, 6th Great Lakes Symposium on VLSI, 1996.

	BibTex	x
	@article{ 10.1109/GLSV.1996.497619, author = {Bradley S. Carlson and C.Y. Roger Chen and Dikran Meliksetian}, title = {Transistor Chaining in CMOS Leaf Cells of Planar Topology}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1996}, isbn = {0-8186-7502-0}, pages = {0194}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497619}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Transistor Chaining in CMOS Leaf Cells of Planar Topology SN - 0-8186-7502-0 SP EP A1 - Bradley S. Carlson, A1 - C.Y. Roger Chen, A1 - Dikran Meliksetian, PY - 1996 VL - 0 JA - Great Lakes Symposium on VLSI ER -

Bradley S. Carlson, Dept. of EEDept. of ECE SUNY at Stony Brook Syracuse University

C.Y. Roger Chen, Dept. of EEDept. of ECE SUNY at Stony Brook Syracuse University

Dikran Meliksetian, Dept. of EEDept. of ECE SUNY at Stony Brook Syracuse University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497619

A technique for chaining the transistors in the layouts of static CMOS leaf cells is presented and analyzed. This new method is superior to existing techniques, since it can operate on a more general class of circuits and is very efficient. It is shown that the layout width of a CMOS leaf cell can be significantly reduced (nearly 40\% in the average case) by transistor chaining. Moreover, more than half of the switching functions of four variables have optimal CMOS circuit implementations with non-series/parallel topologies. Therefore, the use of non-series/parallel circuits can have a positive global impact on layout area and performance. The transistor chaining technique presented in this paper produces the optimal solution for 82% of the circuits tested, and has linear time complexity.

Citation:

Bradley S. Carlson, C.Y. Roger Chen, Dikran Meliksetian, "Transistor Chaining in CMOS Leaf Cells of Planar Topology," glsvlsi, pp.0194, 6th Great Lakes Symposium on VLSI, 1996

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