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6th Great Lakes Symposium on VLSI
FPGA-based high performance page layout segmentation
Ames, IA
March 22-March 23
ISBN: 0-8186-7502-0
ASCII Text
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N.K. Ratha, A.K. Jain, D.T. Rover, "FPGA-based high performance page layout segmentation," Great Lakes Symposium on VLSI, pp. 0029, 6th Great Lakes Symposium on VLSI, 1996.
 
 
BibTex
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@article{ 10.1109/GLSV.1996.497588,
author = {N.K. Ratha and A.K. Jain and D.T. Rover},
title = {FPGA-based high performance page layout segmentation},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1996},
isbn = {0-8186-7502-0},
pages = {0029},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497588},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - FPGA-based high performance page layout segmentation
SN - 0-8186-7502-0
SP
EP
A1 - N.K. Ratha,
A1 - A.K. Jain,
A1 - D.T. Rover,
PY - 1996
KW - image segmentation; field programmable gate arrays; parallel processing; Splash 2; text; page layout segmentation algorithm; FPGA array processor; Xilinx synthesis tool; 5 GHz; 1024 pixel
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
N.K. Ratha, Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
A.K. Jain, Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
D.T. Rover, Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
Abstract: A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2-an FPGA-based array processor. The speed as determined by the Xilinx synthesis tools projects an application speed of 5 MHz. For documents of size 1,024 X 1,024 pixels, a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved.
Index Terms:
image segmentation; field programmable gate arrays; parallel processing; Splash 2; text; page layout segmentation algorithm; FPGA array processor; Xilinx synthesis tool; 5 GHz; 1024 pixel
Citation:
N.K. Ratha, A.K. Jain, D.T. Rover, "FPGA-based high performance page layout segmentation," glsvlsi, pp.0029, 6th Great Lakes Symposium on VLSI, 1996
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