CSDL - Proceedings G

Message from the Steering Committee Chair (PDF)

pp. x

Program Chair's Message (PDF)

pp. xi

Conference Chairs (PDF)

pp. xii

Keynote Address: 21st Century Gigascale Integration (GSI) (PDF)

James D. Meindl

pp. xiii

Reviewers List (PDF)

pp. xiv

Panel: Low Power versus High Speed: Can you have both? (PDF)

pp. xv

Session 1A: Synthesis I

Uniform area timing-driven circuit implementation (Abstract)

D. Karayiannis, Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA

S. Tragoudas, Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA

pp. 2

PDF

Optimization using implicit techniques for industrial designs (Abstract)

F. Poirot, Compass Design Autom., Sophia-Antipolis, France

G. Tarroux, Compass Design Autom., Sophia-Antipolis, France

R. Roane, Compass Design Autom., Sophia-Antipolis, France

pp. 8

PDF

Optimal technology mapping for single output cells (Abstract)

U. Hinsberger, Lehrstuhl fur Tech. Inf., Wurzburg Univ., Germany

R. Kolla, Lehrstuhl fur Tech. Inf., Wurzburg Univ., Germany

pp. 14

PDF

Session 1B: Analog VLSI

A Differential Model Approach To Analog Design Automation (Abstract)

D. J. Klein, School of Electrical Engineering and Computer Science

M. L. Manwaring, School of Electrical Engineering and Computer Science

pp. 22

PDF

A new approach for modeling and optimization of analog systems (Abstract)

E. Penn, New Haven Univ., West Haven, CT, USA

L. Schelovanov, New Haven Univ., West Haven, CT, USA

pp. 28

PDF

A scalable analog architecture for neural networks with on-chip learning and refreshing (Abstract)

B.A. Alhalabi, Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA

M. Bayoumi, Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA

pp. 33

PDF

Session 2A: Physical Design I

Bus minimization and scheduling of multi-chip systems (Abstract)

M. Sheliga, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA

E. Hsing-Mean Sha, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA

pp. 40

PDF

Thumbnail rectilinear Steiner trees (Abstract)

J.L. Ganley, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA

J.P. Cohoon, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA

pp. 46

PDF

A two-stage simulated annealing methodology (Abstract)

J.M. Varanelli, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA

J.P. Cohoon, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA

pp. 50

PDF

Optimizing wiring space in slicing floorplans (Abstract)

J.T. Mowchenko, Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada

Y. Yang, Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada

pp. 54

PDF

Session 2B: Low Power Design

Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks (Abstract)

E. Macii, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

M. Poncino, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

pp. 60

PDF

Design and analysis of a low-power energy-recovery adder (Abstract)

N. Tzartzanis, Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA

W.C. Athas, Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA

pp. 66

PDF

Coding a terminated bus for low power (Abstract)

M.R. Stan, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA

W.P. Burleson, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA

pp. 70

PDF

Circuit/architecture for low-power high-performance 32-bit adder (Abstract)

I.S. Abu-Khater, VLSI Res. Group, Waterloo Univ., Ont., Canada

A. Bellaouar, VLSI Res. Group, Waterloo Univ., Ont., Canada

M.I. Elmasry, VLSI Res. Group, Waterloo Univ., Ont., Canada

R.H. Yan, VLSI Res. Group, Waterloo Univ., Ont., Canada

pp. 74

PDF

Session 3A: Synthesis II

Symbolic execution of data paths (Abstract)

C. Monahan, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

F. Brewer, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

pp. 80

PDF

Specification and synthesis of bounded indirection (Abstract)

M.E. Tuna, Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA

K. Rath, Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA

S.D. Johnson, Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA

pp. 86

PDF

Synthesis of SEU-tolerant ASICs using concurrent error correction (Abstract)

H. Hollander, Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA

B.S. Carlson, Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA

T.D. Bennett, Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA

pp. 90

PDF

Scheduling conditional data-flow graphs with resource sharing (Abstract)

J. Siddhiwala, Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

Liang-Fang Chao, Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

pp. 94

PDF

Session 3B: Verification

Automated verification of temporal properties specified as state machines in VHDL (Abstract)

Y.V. Hoskote, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA

J.A. Abraham, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA

D.S. Fussell, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA

pp. 100

PDF

Partitioning transition relations efficiently and automatically (Abstract)

Z. Zhou, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada

X. Song, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada

F. Corella, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada

E. Cerny, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada

M. Langevin, Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada

pp. 106

PDF

Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions (Abstract)

E. Macci, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

M. Poncino, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

pp. 112

PDF

Session 4A: Physical Design II

An efficient building block layout methodology for compact placement (Abstract)

N.G. Bourbakis, T.J. Watson Sch. of Appl. Sci., Binghamton Univ., NY, USA

M. Mortazavi, T.J. Watson Sch. of Appl. Sci., Binghamton Univ., NY, USA

pp. 118

PDF

Performance driven standard-cell placement using the genetic algorithm (Abstract)

H. Youssef, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

S.M. Sait, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

K. Nassar, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

M.S.T. Benten, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

pp. 124

PDF

An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement (Abstract)

Jin-Tai Yan, Department of Computer and Information Science

pp. 128

PDF

Priority driven channel pin assignment (Abstract)

I. Peters, Inst. fur Inf., Halle Univ., Germany

P. Molitor, Inst. fur Inf., Halle Univ., Germany

pp. 132

PDF

Session 4B: Architecture and Design I

A systolic algorithm and architecture for image thinning (Abstract)

N. Ranganathan, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA

K.B. Doreswamy, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA

pp. 138

PDF

Analyzing and verifying locally clocked circuits with the concurrency workbench (Abstract)

G. Baulch, Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA

D. Hemmendinger, Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA

C. Traver, Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA

pp. 144

PDF

Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs (Abstract)

Jae-Tack Yoo, Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA

E. Brunvand, Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA

K.F. Smith, Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA

pp. 148

PDF

A local clocking approach for self-timed datapath designs (Abstract)

S. Kim, Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA

R. Sridhar, Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA

pp. 152

PDF

Session 5A: Synthesis III

A soft computing approach to hardware software codesign (Abstract)

V. Catania, Istituto di Inf. e Telecommun., Catania Univ., Italy

N. Fiorito, Istituto di Inf. e Telecommun., Catania Univ., Italy

M. Malgeri, Istituto di Inf. e Telecommun., Catania Univ., Italy

M. Russo, Istituto di Inf. e Telecommun., Catania Univ., Italy

pp. 158

PDF

Technology mapping algorithms for sequential circuits using look-up table based FPGAS (Abstract)

S. Habib, Dept. of Comput. Sci., Graduate Sch. of City Univ. of New York, NY, USA

Quan Xu, Dept. of Comput. Sci., Graduate Sch. of City Univ. of New York, NY, USA

pp. 164

PDF

Modeling of communication protocols in VHDL (Abstract)

A. Assi, Ecole Polytech., Montreal, Que., Canada

B. Kaminska, Ecole Polytech., Montreal, Que., Canada

pp. 168

PDF

Using EDIF for software generation (Abstract)

M.J. Van Der Westhuizen, Dept. of Electr. Eng., Natal Univ., Durban, South Africa

R.G. Harley, Dept. of Electr. Eng., Natal Univ., Durban, South Africa

D.C. Levy, Dept. of Electr. Eng., Natal Univ., Durban, South Africa

D.R. Woodward, Dept. of Electr. Eng., Natal Univ., Durban, South Africa

pp. 172

PDF

Session 5B: Testing

A protocol extraction strategy for control point insertion in design for test of transition signaling circuits (Abstract)

H.E. Li, Dept. of Comput. Sci., Concordia Univ., Montreal, Que., Canada

P.N. Lam, Dept. of Comput. Sci., Concordia Univ., Montreal, Que., Canada

pp. 178

PDF

Statistical estimation of delay fault detectabilities and fault grading (Abstract)

Zaifu Zhang, Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada

R.D. McLeod, Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada

G.E. Bridges, Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada

pp. 184

PDF

Test application time reduction for scan based sequential circuits (Abstract)

Hao Zheng, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

K.K. Saluja, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

R. Jain, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

pp. 188

PDF

Pseudo-random behavioral ATPG (Abstract)

A.-L. Courbis, LG12P, EMA-EERIE, Nimes, France

J.-F. Santucci, LG12P, EMA-EERIE, Nimes, France

pp. 192

PDF

Session 6A: Physical Design III

Fast algorithm for performance-oriented Steiner routing (Abstract)

M. Borah, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

pp. 198

PDF

On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing (Abstract)

A.D. Johnson, Dept. of Electr. Eng., Toledo Univ., OH, USA

pp. 204

PDF

OPRON: a new approach to planar OTC routing (Abstract)

S. Danda, Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA

S. Madhwapathy, Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA

N. Sherwani, Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA

A. Sureka, Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA

pp. 208

PDF

Parallel hierarchical global routing for general cell layout (Abstract)

S. Khanna, Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

S. Gao, Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

K. Thulasiraman, Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

pp. 212

PDF

Session 6B: Asynchronous Circuits

Improving self-timed pipeline ring performance through the addition of buffer loops (Abstract)

Hai Zhao, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA

N.M. Sabine, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA

Edwin Hsing-Mean Sha, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA

pp. 218

PDF

Scan testing of asynchronous sequential circuits (Abstract)

O.A. Petlin, Dept. of Comput. Sci., Oxford Univ., UK

S.B. Furber, Dept. of Comput. Sci., Oxford Univ., UK

pp. 224

PDF

A new look at the conditions for the synthesis of speed-independent circuits (Abstract)

E. Pastor, Dept. of Comput. Archit., universitat Politecnica de Catlunya, Barcelona, Spain

J. Cortadella, Dept. of Comput. Archit., universitat Politecnica de Catlunya, Barcelona, Spain

O. Roig, Dept. of Comput. Archit., universitat Politecnica de Catlunya, Barcelona, Spain

pp. 230

PDF

Session 7A: VLSI Education

Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT (Abstract)

L.F. Fuller, Dept. of Microelectron. Eng., Rochester Inst. of Technol., NY, USA

C. Kraaijenvanger, Dept. of Microelectron. Eng., Rochester Inst. of Technol., NY, USA

pp. 238

PDF

Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test (Abstract)

H.J. Pottinger, Dept. of Electr. Eng., Missouri Univ., Rolla, MO, USA

Chien-Yuh Lin, Dept. of Electr. Eng., Missouri Univ., Rolla, MO, USA

pp. 242

PDF

Linking fabrication and parametric testing to VLSI design courses (Abstract)

R. Pearson, Dept. of Microelectron. Eng., Rochester Inst. of Technol., NY, USA

pp. 246

PDF

A personal computer based VLSI design curriculum (Abstract)

W.B. Leigh, Div. of Electr. Eng., Alfred Univ., NY, USA

pp. 250

PDF

Session 7B: Architecture and Design II

A scalable shared buffer ATM switch architecture (Abstract)

A. Agrawal, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

A. Raju, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

S. Varadarajan, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

M.A. Bayoumi, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

pp. 256

PDF

ATM burst traffic generator (Abstract)

P.P. Chu, Dept. of Electr. Eng., Cleveland State Univ., OH, USA

pp. 262

PDF

A universal formalization of the effects of threshold voltages for discrete switch-level circuit models (Abstract)

W.H.F.J. Korver, Dept. of Electron. & Electr. Eng., Surrey Univ., Guildford, UK

pp. 266

PDF

Index of Authors (PDF)

pp. 273