The State University of New York at Buffalo
Mar. 16, 1995 to Mar. 18, 1995
S. Khanna , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
S. Gao , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
K. Thulasiraman , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
In this paper we present a parallel global routing algorithm for general cell layout. The algorithm applies a hierarchical decomposition strategy that recursively divides routing problems into simple, independent subproblems for parallel processing. The solution of each subproblem is based on integer programming and network flow optimization. The algorithm is implemented on a shared-memory machine and experiment results on different examples show relative speedup between 4 and 5 for 8 processors. The speedup is achieved without compromising the quality of the routing results.
network routing; VLSI; circuit layout CAD; integrated circuit layout; integer programming; parallel algorithms; parallel hierarchical global routing; general cell layout; routing algorithm; hierarchical decomposition strategy; parallel processing; integer programming; network flow optimization; shared-memory machine
S. Khanna, S. Gao, K. Thulasiraman, "Parallel hierarchical global routing for general cell layout", GLSVLSI, 1995, Great Lakes Symposium on VLSI, Great Lakes Symposium on VLSI 1995, pp. 212, doi:10.1109/GLSV.1995.516055