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The State University of New York at Buffalo
Mar. 16, 1995 to Mar. 18, 1995
ISBN: 0-8186-7035-5
pp: 106
Z. Zhou , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
X. Song , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
F. Corella , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
E. Cerny , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
M. Langevin , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
ABSTRACT
Multiway Decision Graphs (MDGs) have been recently proposed as an efficient representation of Extended Finite State Machines (EFSMs), suitable for automatic hardware verification of Register Transfer Level (RTL) designs. We report here on the results of our research into automatic partitioning of state transition relations described using MDGs. The objective is to achieve the maximum possible performance during an abstract implicit state enumeration procedure that is at the basis of our automatic verification method.
INDEX TERMS
logic partitioning; logic CAD; graph theory; state estimation; finite state machines; automatic partitioning; state transition relations; multiway decision graphs; abstract implicit state enumeration procedure; automatic verification method; extended finite state machines; register transfer level designs
CITATION
Z. Zhou, X. Song, F. Corella, E. Cerny, M. Langevin, "Partitioning transition relations efficiently and automatically", GLSVLSI, 1995, Great Lakes Symposium on VLSI, Great Lakes Symposium on VLSI 1995, pp. 106, doi:10.1109/GLSV.1995.516034
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