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6th Symposium on the Frontiers of Massively Parallel Computation
Processor autonomy and its effect on parallel program execution
Annapolis, Maryland
March 27-March 31
ISBN: 0-8186-7551-9
ASCII Text
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D.M. Hawver, G.B. Adams, III, "Processor autonomy and its effect on parallel program execution," Frontiers of Massively Parallel Processing, Symposium on the, pp. 144, 6th Symposium on the Frontiers of Massively Parallel Computation, 1996.
 
 
BibTex
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@article{ 10.1109/FMPC.1996.558071,
author = {D.M. Hawver and G.B. Adams, III},
title = {Processor autonomy and its effect on parallel program execution},
journal ={Frontiers of Massively Parallel Processing, Symposium on the},
volume = {0},
year = {1996},
issn = {1088-4955},
pages = {144},
doi = {http://doi.ieeecomputersociety.org/10.1109/FMPC.1996.558071},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Frontiers of Massively Parallel Processing, Symposium on the
TI - Processor autonomy and its effect on parallel program execution
SN - 1088-4955
SP
EP
A1 - D.M. Hawver,
A1 - G.B. Adams, III,
PY - 1996
KW - parallel programming; processor autonomy; processing element; parallel computer; parallel program execution; parallel architecture taxonomy; multiple data address streams; multiple data value streams; multiple instruction address streams; multiple instruction value streams; mappings; dynamic reassignment; parallel program performance evaluation; sorting algorithms; indirect addressing; branch selection
VL - 0
JA - Frontiers of Massively Parallel Processing, Symposium on the
ER -
 
D.M. Hawver, Annapolis Micro Syst., MD, USA
G.B. Adams, III, Annapolis Micro Syst., MD, USA
Processor autonomy is the potential of a processing element in a parallel computer to act differently from other processors during execution. A new parallel architecture taxonomy is presented that includes the necessary and sufficient conditions to achieve processor autonomy. Processor autonomy is possible when multiple data address, data value, instruction address, or instruction value streams are available. Parallel program execution can be significantly aided by processor autonomy, allowing various mappings and dynamic reassignment of PEs to streams. Parallel program performance is evaluated for several sorting algorithms using one form of data address autonomy, indirect addressing, and one form of instruction value autonomy, branch selection.
Index Terms:
parallel programming; processor autonomy; processing element; parallel computer; parallel program execution; parallel architecture taxonomy; multiple data address streams; multiple data value streams; multiple instruction address streams; multiple instruction value streams; mappings; dynamic reassignment; parallel program performance evaluation; sorting algorithms; indirect addressing; branch selection
Citation:
D.M. Hawver, G.B. Adams, III, "Processor autonomy and its effect on parallel program execution," frontiers, pp.144, 6th Symposium on the Frontiers of Massively Parallel Computation, 1996
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