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2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines
Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA
Toronto, Ontario Canada
April 29-May 01
ISBN: 978-0-7695-4699-5
| ASCII Text | x | ||
| Eduardo Gudis, Gooitzen van der Wal, Sujit Kuthirummal, Sek Chai, "Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 29-32, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, 2012. | |||
| BibTex | x | ||
| @article{ 10.1109/FCCM.2012.15, author = {Eduardo Gudis and Gooitzen van der Wal and Sujit Kuthirummal and Sek Chai}, title = {Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {2012}, isbn = {978-0-7695-4699-5}, pages = {29-32}, doi = {http://doi.ieeecomputersociety.org/10.1109/FCCM.2012.15}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA SN - 978-0-7695-4699-5 SP29 EP32 A1 - Eduardo Gudis, A1 - Gooitzen van der Wal, A1 - Sujit Kuthirummal, A1 - Sek Chai, PY - 2012 KW - FPGA KW - Embedded Computer Vision KW - Stereo KW - Image Processing KW - Multi-Resolution KW - Robotics KW - Augmented Reality KW - Visual Navigation VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2012.15
High-performance dense stereo is a critical component of computer vision applications like 3D reconstruction, robot navigation, and augmented reality. In this paper, we present a low-power, high performance FPGA implementation of a stereo algorithm suitable for embedded real-time platforms. The design is sca lable for higher resolution images and frame rates and supporting different cameras and application requirements. We achieve this by designing highly parallel computation cores with very efficient memory access to the image data. Using a prototype board, we demonstrate real-time stereo processing with 640x480 pixel GigE Vision cameras at 30 frames per second. We show that this FPGA design is 10 times lower power, more scalable and has lower latency, as compared to a GPU based implementation of the same ster eo algorithm.
Index Terms:
FPGA, Embedded Computer Vision, Stereo, Image Processing, Multi-Resolution, Robotics, Augmented Reality, Visual Navigation
Citation:
Eduardo Gudis, Gooitzen van der Wal, Sujit Kuthirummal, Sek Chai, "Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA," fccm, pp.29-32, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, 2012
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