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2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs
Charlotte, North Carolina, USA
May 02-May 04
ISBN: 978-0-7695-4056-6
The latest generation of FPGA devices offers huge resource counts that provide the headroom to implement large-scale and complex systems. However, this poses increasing challenges for the designer, not just because of pure size and complexity, but also to harness effectively the flexibility and programmability of the FPGA. A central issue is the need to integrate modules (IP blocks) from diverse sources to promote modular design and reuse. In this paper, we introduce ShapeUp: a high-level approach for designing systems by interconnecting modules, which gives a ‘plug and play’ look and feel to the designer and is supported by tools that carry out implementation and verification functions. The emphasis is on the inter-module connections and abstracting the communication patterns that are typical between modules – for example, the streaming of data that is common in many FPGA based DSP or networking systems, or the reading and writing of data to and from memory modules. The details of wiring and signaling are hidden from view, via metadata associated with individual modules. The ShapeUp tool suite includes an implementation capability that automatically generates wiring between blocks, possibly including additional bridging blocks, and a simulation capability that allows multi-level verification of systems of interconnected modules. The methodology and tools have been validated on Xilinx customer design projects.
Index Terms:
Modular system design, FPGA, interface abstraction, high-level design methodology
Citation:
Christopher Neely, Gordon Brebner, Weijia Shang, "ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs," fccm, pp.141-148, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010
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