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2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs
Charlotte, North Carolina, USA
May 02-May 04
ISBN: 978-0-7695-4056-6
The architecture of Xilinx FPGAs, has changed remarkable with respect to their ability to implement runtime reconfigurable systems throughout the last generations. This paper will discuss these changes and reveal an on-FPGA communication architecture that is especially tailored to Xilinx Virtex-5 FPGAs. With this architecture, modules can be integrated in a two-dimensional grid with more than a hundred of individual tiles while allowing a throughput of several GB/s to reconfigurable modules.
Index Terms:
Partial Runtime reconfiguration, Virtex-5, on-FPGA communication
Citation:
Dirk Koch, Christian Beckhoff, Jim Torrison, "Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs," fccm, pp.69-72, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010
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