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2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration
Charlotte, North Carolina, USA
May 02-May 04
ISBN: 978-0-7695-4056-6
SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU), which is induced by radiation effect. This paper presents a technique for ensuring reliable softcore processor implementation on SRAM-based FPGAs. Although an FPGA is susceptible to SEUs, these faults can be corrected as a result of its reconfigurability. We propose techniques for SEU mitigation and recovery of a softcore processor using triple modular redundancy (TMR) and partial reconfiguration (PR) with state synchronization. By carrying out an experiment, we confirm that a faulty softcore processor can be recovered and synchronized with other softcore processors. The proposed technique requires 4.315 times the resource usage and 62.491% of the operating frequency of the base processor. However, the proposed recovery process only takes 6 μs under TMR and PR. As a result of reliability estimation, the proposed system achieved about 2.713 times longer MTBF comparing with the previous system.
Index Terms:
SEU, TMR, Partial Reconfiguration, Softcore Processor, ECC
Citation:
Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi, "Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration," fccm, pp.47-54, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010
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