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2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Accelerating the Nonuniform Fast Fourier Transform Using FPGAs
Charlotte, North Carolina, USA
May 02-May 04
ISBN: 978-0-7695-4056-6
We present an FPGA accelerator for the Non-uniform Fast Fourier Transform, which is a technique to reconstruct images from arbitrarily sampled data. We accelerate the compute-intensive interpolation step of the NuFFT Gridding algorithm by implementing it on an FPGA. In order to ensure efficient memory performance, we present a novel FPGA implementation for Geometric Tiling based sorting of the arbitrary samples. The convolution is then performed by a novel Data Translation architecture which is composed of a multi-port local memory, dynamic coordinate-generator and a plug-and-play kernel pipeline. Our implementation is in single-precision floating point and has been ported onto the BEE3 platform. Experimental results show that our FPGA implementation can generate fairly high performance without sacrificing flexibility for various data-sizes and kernel functions. We demonstrate up to 8X speedup and up to 27 times higher performance-per-watt over a comparable CPU implementation and up to 20% higher performance-per-watt when compared to a relevant GPU implementation.
Index Terms:
NuFFT, interpolation, convolution, BEE3, Geometric Tiling
Citation:
Srinidhi Kestur, Sungho Park, Kevin M. Irick, Vijaykrishnan Narayanan, "Accelerating the Nonuniform Fast Fourier Transform Using FPGAs," fccm, pp.19-26, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010
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