CSDL - Proceedings F

Session 1: Applications 1

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Efficient Hardware Data Mining with the Apriori Algorithm on FPGAs (Abstract)

Zachary K. Baker, University of Southern California

Viktor K. Prasanna, University of Southern California

pp. 3-12

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A Novel 2D Filter Design Methodology for Heterogeneous Devices (Abstract)

Christos-Savvas Bouganis, Imperial College London

George A. Constantinides, Imperial College London

Peter Y. K. Cheung, Imperial College London

pp. 13-22

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Prototyping Architectural Support for Program Rollback Using FPGAs (Abstract)

Radu Teodorescu, University of Illinois at Urbana-Champaign

Josep Torrellas, University of Illinois at Urbana-Champaign

pp. 23-32

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Session 2: Architecture

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Zion Kwok, University of British Columbia

Steven J. E. Wilton, University of British Columbia

pp. 35-44

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Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-on-Chip (Abstract)

Francesco Lertora, STMicroelectronics

Michele Borgatti, STMicroelectronics

pp. 45-54

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Session 3: Tools 1

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A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation (Abstract)

Roman Lysecky, University of California at Riverside

Frank Vahid, University of California at Riverside

Sheldon X.-D. Tan, University of California at Riverside

pp. 57-62

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Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller (Abstract)

Lesley Shannon, University of Toronto

Paul Chow, University of Toronto

pp. 63-72

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Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable Architectures (Abstract)

Pedro C. Diniz, University of Southern California

pp. 73-82

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Session 4: Graphics

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FPGA Particle Graphics Hardware (Abstract)

John Sachs Beeckler, McGill University

Warren J. Gross, McGill University

pp. 85-94

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Reconfigurable Designs for Radiosity (Abstract)

Paul Baker, Imperial College

Tim Todman, Imperial College

Henry Styles, Imperial College

Wayne Luk, Imperial College

pp. 95-104

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Session 5: Applications 2

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Hardware Factorization Based on Elliptic Curve Method (Abstract)

Martin Šimka, Technical University of Košice

Jan Pelzl, Ruhr University Bochum

Thorsten Kleinjung, University of Bonn

Jens Franke, University of Bonn

Christine Priplata, EDIZONE GmbH

Colin Stahlke, EDIZONE GmbH

Miloš Drutarovský, Technical University of Košice

Viktor Fischer, Université Jean Monnet

pp. 107-116

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Metropolitan Road Traffic Simulation on FPGAs (Abstract)

Justin L. Tripp, Los Alamos National Laboratory

Henning S. Mortveit, Los Alamos National Laboratory

Anders Å. Hansson, Los Alamos National Laboratory

Maya Gokhale, Los Alamos National Laboratory

pp. 117-126

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Time Domain Numerical Simulation for Transient Waves on Reconfigurable Coprocessor Platform (Abstract)

Chuan He, Texas A&M University

Wei Zhao, Texas A&M University

Mi Lu, Texas A&M University

pp. 127-136

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COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft Processors (Abstract)

Session 6: Run Time

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Jingzhao Ou, University of Southern California

Viktor K. Prasanna, University of Southern California

pp. 139-148

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An Execution Environment for Reconfigurable Computing (Abstract)

Wenyin Fu, University of Wisconsin at Madison

Katherine Compton, University of Wisconsin at Madison

pp. 149-158

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Session 7: Arithmetic

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Higher Radix Floating-Point Representations for FPGA-Based Arithmetic (Abstract)

Bryan Catanzaro, Brigham Young University

Brent Nelson, Brigham Young University

pp. 161-170

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An Analysis of the Double-Precision Floating-Point FFT on FPGAs (Abstract)

K. Scott Hemmert, Sandia National Laboratories

Keith D. Underwood, Sandia National Laboratories

pp. 171-180

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A Comparison of Floating Point and Logarithmic Number Systems for FPGAs (Abstract)

Michael Haselman, University of Washington

Michael Beauchamp, University of Washington

Aaron Wood, University of Washington

Scott Hauck, University of Washington

Keith Underwood, Sandia National Labratories

K. Scott Hemmert, Sandia National Labratories

pp. 181-190

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Session 8: Device Architecture

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Terrestrial-Based Radiation Upsets: A Cautionary Tale (Abstract)

Heather Quinn, Los Alamos National Laboratory

Paul Graham, Los Alamos National Laboratory

pp. 193-202

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Automating the Layout of Reconfigurable Subsystems Using Circuit Generators (Abstract)

Shawn Phillips, University of Washington

Scott Hauck, University of Washington

pp. 203-212

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Session 9: Networking

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Fast Reconfiguring Deep Packet Filter for 1+ Gigabit Network (Abstract)

Young H. Cho, University of California at Los Angeles

William H. Mangione-Smith, University of California at Los Angeles

pp. 215-224

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A Framework for Rule Processing in Reconfigurable Network Systems (Abstract)

Michael Attig, Washington University in Saint Louis

John Lockwood, Washington University in Saint Louis

pp. 225-234

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A Signature Match Processor Architecture for Network Intrusion Detection (Abstract)

Janardhan Singaraju, University of Connecticut

Long Bu, University of Connecticut

John A. Chandy, University of Connecticut

pp. 235-242

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Session 10: Tools 2

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Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation (Abstract)

José Gabriel F. Coutinho, Imperial College London

Jun Jiang, Imperial College London

Wayne Luk, Imperial College London

pp. 245-254

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Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters (Abstract)

Hristo Nikolov, Leiden University

Todor Stefanov, Leiden University

Ed Deprettere, Leiden University

pp. 255-263

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Posters

A BIST Approach for Testing FPGAs Using JBITS (PDF)

M. Y. Niamat, University of Toledo

Surya S. Hejeebu, University of Toledo

M. Alam, University of Toledo

pp. 267-268

Preliminary Report: FPGA Acceleration of Molecular Dynamics Computations (PDF)

Yongfeng Gu, Boston University

Tom Van Court, Boston University

Douglas DiSabello, Boston University

Martin C. Herbordt, Boston University

pp. 269-270

A High-Performance Asynchronous FPGA: Test Results (PDF)

David Fang, Cornell University

John Teifel, Cornell University

Rajit Manohar, Cornell University

pp. 271-272

Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures (PDF)

Sudarshan Banerjee, University of California at Irvine

Elaheh Bozorgzadeh, University of California at Irvine

Nikil Dutt, University of California at Irvine

pp. 273-274

RAVIOLI — Reconfigurable Arithmetic Variable-Precision Implementations of On-Line Instructions (PDF)

Robert McIlhenny, California State University at Northridge

Miloš D. Ercegovac, Univesity of California at Los Angeles

pp. 275-276

FIFO Communication Models in Operating Systems for Reconfigurable Computing (PDF)

J. A. Williams, University of Queensland

N. W. Bergmann, University of Queensland

X. Xie, University of Queensland

pp. 277-278

Astrophysical Hydrodynamics Simulations on a Reconfigurable System (PDF)

Naohito Nakasato, Institute of Physical and Chemical Research

Tsuyoshi Hamada, Institute of Physical and Chemical Research

pp. 279-280

Post Synthesis Level Power Modeling of FPGAs (PDF)

Matthew French, University of Southern California

Li Wang, University of Southern California

Tyler Anderson, Brigham Young University

Michael Wirthlin, Brigham Young University

pp. 281-282

FPGA-Based CDMA Switch for Networks-on-Chip (PDF)

Daewook Kim, University of Minnesota

Manho Kim, University of Minnesota

Gerald E. Sobelman, University of Minnesota

pp. 283-284

Design of Networked Reconfigurable Encryption Engine (PDF)

Shakith Fernando, National University of Singapore

Ha Yajun, National University of Singapore

pp. 285-286

A Virtual Machine for Merit-Based Runtime Reconfiguration (PDF)

Brian Greskamp, University of Illinois at Urbana-Champaign

Ron Sass, University of Kansas

pp. 287-288

Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC (PDF)

Mark Holland, University of Washington

Scott Hauck, University of Washington

pp. 289-290

The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture (PDF)

Xin Jia, University of Cincinnati

Ranga Vemuri, University of Cincinnati

pp. 291-292

Optimizing Technology Mapping for FPGAs Using CAMs (PDF)

Joshua M. Lucas, University of Pittsburgh

Raymond Hoare, University of Pittsburgh

Alex K. Jones, University of Pittsburgh

pp. 293-294

An Architecture for Video Compression Based on the SCAN Algorithm (PDF)

H. Sofikitis, Technical University of Crete

K. Roumpou, Technical University of Crete

A. Dollas, Technical University of Crete

N. Bourbakis, Wright State University

pp. 295-296

An Open TCP/IP Core for Reconfigurable Logic (PDF)

Apostolos Dollas, Technical University of Crete

Ioannis Ermis, Technical University of Crete

Iosif Koidis, Technical University of Crete

Ioannis Zisis, Technical University of Crete

Christopher Kachris, Technical University of Crete

pp. 297-298

Mutable Codesign for Embedded Protocol Processing (PDF)

Todd Sproull, Washington University in Saint Louis

Gordon Brebner, Xilinx, Inc.

Christopher Neely, Xilinx, Inc.

pp. 299-300

Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems (PDF)

M. D. Galanis, University of Patras

G. Dimitroulakos, University of Patras

C. E. Goutis, University of Patras

pp. 301-302

An Embedded Reconfigurable Datapath for SoC (PDF)

Andrea Lodi, University of Bologna

Luca Ciccarelli, University of Bologna

Claudio Mucci, University of Bologna

Roberto Giansante, University of Bologna

Andrea Cappelli, University of Bologna

Mario Toma, STMicroelectronics

pp. 303-304

Systolic Architecture for Computing the Discrete Fourier Transform on FPGAs (PDF)

J. Greg Nash, Centar

pp. 305-306

Hardware Solution to Java Compressed Heap (PDF)

Mayumi Kato, University of Texas at San Antonio

Chia-Tien Dan Lo, University of Texas at San Antonio

pp. 307-308

A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms (PDF)

Petersen F. Curt, EM Photonics, Inc.

James P. Durbano, EM Photonics, Inc.

Fernando E. Ortiz, EM Photonics, Inc.

John R. Humphrey, EM Photonics, Inc.

Dennis W. Prather, University of Delaware

pp. 309-310

Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA (Abstract)

Arash Hariri, Amirkabir University of Technology

Reza Rastegar, Amirkabir University of Technology

Morteza Saheb Zamani, Amirkabir University of Technology

Mohammad R. Meybodi, Amirkabir University of Technology

pp. 311-314

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Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor (PDF)

Hideharu Amano, Keio University

Shohei Abe, Keio University

Yohei Hasegawa, Keio University

Katsuaki Deguchi, Keio University

Masayasu Suzuki, Keio University

pp. 315-316

A System-on-Programmable Chip Approach for MIMO Sphere Decoder (PDF)

Jing Ma, University of New Orleans

Xinming Huang, University of New Orleans

pp. 317-318

The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform (PDF)

Christophe Bobda, University of Erlangen-Nuremberg

Mateusz Majer, University of Erlangen-Nuremberg

Ali Ahmadinia, University of Erlangen-Nuremberg

Thomas Haller, University of Erlangen-Nuremberg

André Linarth, University of Erlangen-Nuremberg

Jürgen Teich, Braunschweig University of Technology

Jan van der Veen, Braunschweig University of Technology

pp. 319-320

Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA Platforms (PDF)

Alberto Donato, Politecnico di Milano

Fabrizio Ferrandi, Politecnico di Milano

Massimo Redaelli, Politecnico di Milano

Marco D. Santambrogio, Politecnico di Milano

Donatella Sciuto, Politecnico di Milano

pp. 321-322

High-Performance FPGA-Based General Reduction Methods (PDF)

Gerald R. Morris, University of Southern California

Ling Zhuo, University of Southern California

Viktor K. Prasanna, University of Southern California

pp. 323-324

Core-Based Methodology: An Automated Approach for Implementing a Complete System from Algorithms to a Heterogeneous Network including FPGAs (PDF)

Jasmine Lam, QinetiQ

John McAllister, Queens University

Jennifer Dudley, QinetiQ

pp. 325-326

The DARPA Dynamic Programming Benchmark on a Reconfigurable Computer. (PDF)

Luis E. Cordova, University of South Carolina

Duncan A. Buell, University of South Carolina

Sreesa Akella, University of South Carolina

pp. 327-328

Massively Parallel Processors Generator for Reconfigurable System (PDF)

Tsuyoshi Hamada, Institute of Physical and Chemical Research

Naohito Nakasato, Institute of Physical and Chemical Research

pp. 329-330

FPGA-Based Vector Processing for Solving Sparse Sets of Equations (PDF)

Muhammad Z. Hasan, New Jersey Institute of Technology

Sotirios G. Ziavras, New Jersey Institute of Technology

pp. 331-332

Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures (PDF)

Joseph Zambreno, Northwestern University

Dan Honbo, Northwestern University

Alok Choudhary, Northwestern University

pp. 333-334

On Distributed Reconfigurable Systems: Open Problems and Some Initial Solutions (PDF)

Apostolos Dollas, Technical University of Crete

Dionissios Efstathiou, Technical University of Crete

Georgios Vernardos, Technical University of Crete

Elias Polytarchos, Technical University of Crete

Konstantinos Kazakos, Technical University of Crete

pp. 335-336

Author Index

Author Index (PDF)

pp. 337-338