New reconfigurable computing platforms are introduced to overcome some of the limitations of microprocessors and fine-grained reconfigurable devices (e.g., FPGAs). One of the new promising architectures are Special-Purpose Programmable (SPP) or Configurable System-on-Chip (CSoC) solutions. They were designed to provide high performance for real-time signal processing and for a broad range of applications exhibiting high degrees of parallelism. The new CSoC proposed here offers a programming model and provides high flexibility and adaptability by employing a micro Task Controller (mTC). It can be forward compatible as the micro Task Controller program can be reused for other CSoC architecture families which differs in the number of reconfigurable processing cells. The architecture is modular and hierarchically structured to approve an efficient mapping of applications and provides a straightforward path for scaling and design complexity reduction. The architecture composition, the system control mechanism, the programming paradigm as well as algorithms mapping and performance analysis are presented.