CSDL - Proceedings F

Session 1: Applications

A High I/O Reconfigurable Crossbar Switch (Abstract)

Steve Young, Xilinx Inc

Peter Alfke, Xilinx Inc

Colm Fewer, Xilinx Ireland

Scott McMillan, Xilinx Inc

Brandon Blodget, Xilinx Inc

Delon Levi, Xilinx Inc

pp. 3

PDF

Congruential Sieves on a Reconfigurable Computer (Abstract)

Heather A. Wake, University of South Carolina

Duncan A. Buell, University of South Carolina

pp. 11

PDF

Performance Analysis of Fixed, Reconfigurable, and Custom Architectures for the SCAN Image and Video Encryption Algorithm (Abstract)

Apostolos Dollas, Technical University of Crete

Christopher Kachris, Technical University of Crete

Nikolaos Bourbakis, Wright State University

pp. 19

PDF

Session 2: Network Security

Implementation of a Content-Scanning Module for an Internet Firewall (Abstract)

James Moscola, Washington University, St. Louis, MO

John Lockwood, Washington University, St. Louis, MO

Ronald P. Loui, Washington University, St. Louis, MO

Michael Pachos, Washington University, St. Louis, MO

pp. 31

PDF

Compiling Policy Descriptions into Reconfigurable Firewall Processors (Abstract)

T.K. Lee, Imperial College

S. Yusuf, Imperial College

W. Luk, Imperial College

M. Sloman, Imperial College

E. Lupu, Imperial College

N. Dulay, Imperial College

pp. 39

PDF

Session 3: Communication Techniques

Compact FPGA-based True and Pseudo Random Number Generators (Abstract)

K.H. Tsoi, The Chinese University of Hong Kong

K.H. Leung, The Chinese University of Hong Kong

P.H.W. Leong, The Chinese University of Hong Kong

pp. 51

PDF

Accelerating Bit Error Rate Testing Using a System Level Design Tool (Abstract)

V. Singh, Xilinx Inc.

A. Root, Xilinx Inc.

E. Hemphill, Xilinx Inc.

N. Shirazi, Xilinx Inc.

J. Hwang, Xilinx Inc.

pp. 62

PDF

A Hardware Gaussian Noise Generator for Channel Code Evaluation (Abstract)

Dong-U Lee, Imperial College London

Wayne Luk, Imperial College London

John Villasenor, University of California Los Angeles

Peter Y.K. Cheung, Imperial College London

pp. 69

PDF

Session 4: Arithmetic

Perturbation Analysis for Word-length Optimization (Abstract)

George A. Constantinides, Imperial College, London

pp. 81

PDF

Improved Small Multiplier Based Multiplication, Squaring and Division (Abstract)

B.R. Lee, Cardiff University

N. Burgess, Cardiff University

pp. 91

PDF

Session 5: Device Architecture

Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable (Abstract)

Benjamin A. Levine, Carnegie Mellon University

Herman H. Schmit, Carnegie Mellon University

pp. 101

PDF

Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development (Abstract)

Ken Eguro, University of Washington, Seattle

Scott Hauck, University of Washington, Seattle

pp. 111

PDF

Asynchronous PipeRench: Architecture and Performance Estimations (Abstract)

Hiroto Kagotani, Okayama University

Herman Schmit, Carnegie Mellon University

pp. 121

PDF

Session 6: Fault Modeling and Recovery

The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets (Abstract)

Michael Wirthlin, Brigham Young University, Provo, UT

Eric Johnson, Brigham Young University, Provo, UT

Nathan Rollins, Brigham Young University, Provo, UT

Michael Caffrey, Los Alamos National Laboratory, Los Alamos, NM

Paul Graham, Los Alamos National Laboratory, Los Alamos, NM

pp. 133

PDF

Adaptive Fault Recovery for Networked Reconfigurable Systems (Abstract)

Weifeng Xu, University of Massachusetts

Ramshankar Ramanarayanan, University of Massachusetts

Russell Tessier, University of Massachusetts

pp. 143

PDF

Session 7: Applications

Gamma-Ray Pulsar Detection using Reconfigurable Computing Hardware (Abstract)

Jan Frigo, Los Alamos National Laboratory

David Palmer, Los Alamos National Laboratory

Maya Gokhale, Los Alamos National Laboratory

Marc Popkin-Paine, Los Alamos National Laboratory

pp. 155

PDF

Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA (Abstract)

A Benkrid, The Queen?s University of Belfast

K Benkrid, The Queen?s University of Belfast

D. Crookes, The Queen?s University of Belfast

pp. 162

PDF

Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines (Abstract)

Heather Quinn, Northeastern University

L.A. Smith King, College of the Holy Cross

Miriam Leeser, Northeastern University

Waleed Meleis, Northeastern University

pp. 173

PDF

Session 8: Arithmetic

Floating Point Unit Generation and Evaluation for FPGAs (Abstract)

Jian Liang, University of Massachusetts

Russell Tessier, University of Massachusetts

Oskar Mencer, Imperial College

pp. 185

PDF

Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs (Abstract)

Xiaojun Wang

Brent E. Nelson

pp. 195

PDF

Session 9: Programming Frameworks

Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures (Abstract)

Pedro C. Diniz, University of Southern California

Joonseok Park, University of Southern California

pp. 207

PDF

Simulation and Synthesis of CSP-based Interprocess Communication (Abstract)

Preston A. Jackson, Brigham Young University

Brad L. Hutchings, Brigham Young University

Justin L. Tripp, Brigham Young University

pp. 218

PDF

Source Level Debugger for the Sea Cucumber Synthesizing Compiler (Abstract)

K. Scott Hemmert, Brigham Young University

Justin L. Tripp, Brigham Young University

Brad L. Hutchings, Brigham Young University

Preston A. Jackson, Brigham Young University

pp. 228

PDF

Session 10: Compilation Techniques

Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications (Abstract)

Jingzhao Ou, University of Southern California

Seonil Choi, University of Southern California

Viktor K. Prasanna, University of Southern California

pp. 241

PDF

Reconfigurable Computing Application Frameworks (Abstract)

Anthony L. Slade, Brigham Young University

Brent E. Nelson, Brigham Young University

Brad L. Hutchings, Brigham Young University

pp. 251

PDF

Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design (PDF)

Posters

P. Banerjee, Northwestern University

D. Bagchi, AccelChip, Inc.

M. Haldar, AccelChip, Inc.

A. Nayak, AccelChip, Inc.

V. Kim, AccelChip, Inc.

R. Uribe, AccelChip, Inc.

pp. 263

Fast Reconfiguration Through Difference Compression (PDF)

Irwin Kennedy, University of Edinburgh

pp. 265

FPGA-based SIMD Processor (PDF)

Stanley Y.C. Li, The Chinese University of Hong Kong

Gap C.K. Cheuk, The Chinese University of Hong Kong

K.H. Lee, The Chinese University of Hong Kong

Philip H.W. Leong, The Chinese University of Hong Kong

pp. 267

Implementation of Three-Dimensional FPGA-Based FDTD Solvers: An Architectural Overview (PDF)

James P. Durbano, EM Photonics, Inc.

Fernando E. Ortiz, University of Delaware

John R. Humphrey, University of Delaware

Dennis W. Prather, University of Delaware

Mark S. Mirotznik, The Catholic University of America

pp. 269

A Pipelined SoPC Architecture for 2.5 Gbps Network Processing (PDF)

Ciaran Toal, Queen?s University Belfast

Sakir Sezer, Queen?s University Belfast

Xing Yu, Queen?s University Belfast

pp. 271

A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs (Abstract)

A. Benkrid, The Queen?s University of Belfast

K. Benkrid, The Queen?s University of Belfast

D. Crookes, The Queen?s University of Belfast

pp. 273

PDF

Recon .gurable High Resolution Network Camera (PDF)

Andrey Filippov, Elphel, Inc.

pp. 276

Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms (PDF)

Javier Resano, Universidad Complutense de Madrid

Diederik Verkest, IMEC vzw; Katholieke Universiteit Leuven

Daniel Mozos, Universidad Complutense de Madrid

Serge Vernalde, IMEC vzw

Francky Catthoor, IMEC vzw; Vrije Universiteit Brussel

pp. 278

A Logic Based Hardware Development Environment (PDF)

S. Belkacemi, The Queen?s University of Belfast

K. Benkrid, The Queen?s University of Belfast

D. Crookes, The Queen?s University of Belfast

pp. 280

Standardizing the Performance Assessment of Reconfigurable Processor Architectures (PDF)

Lesley Shannon, University of Toronto

Paul Chow, University of Toronto

pp. 282

An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs (PDF)

Alex Jones, Northwestern University

Prith Banerjee, Northwestern University

pp. 284

A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NIC (PDF)

Ranjesh G. Jaganathan, Clemson University

Keith D. Underwood, Sandia National Laboratories

Ron Sass, Clemson University

pp. 286

Fabric-Based Systems: Model, Tools, Applications (PDF)

Christophe Wolinski, Los Alamos National Laboratory

Maya Gokhale, Los Alamos National Laboratory

Kevin McCabe, Los Alamos National Laboratory

pp. 288

An Estimation and Simulation Framework for Energy Efficient Design using Platform FPGAs (PDF)

pp. 290

Exploiting Reconfigurable Hardware for Network Security (PDF)

Shaomeng Li, University of Oslo

Jim Torresen, University of Oslo

Oddvar Soraasen, University of Oslo

pp. 292

A Second Generation Embedded Reconfigurable Input Device for Kinetically Challenged Persons (PDF)

Kyprianos Papademetriou, Technical University of Crete

Apostolos Dollas, Technical University of Crete

Stamatios Sotiropoulos, Technical University of Crete

pp. 294

Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations (PDF)

K.R. Shesha Shayee, University of Southern California

Joonseok Park, USC Information Sciences Institute

Pedro C. Diniz, USC Information Sciences Institute

pp. 296

Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines (Abstract)

Joonseok Park, University of Southern California

Pedro C. Diniz, University of Southern California

pp. 297

PDF

Linear Placement for Static / Dynamic Reconfiguration in JBits (PDF)

Vamsi Krishna Marreddy, University of Minnesota, Minneapolis

Sharareh Noorbaloochi, University of Minnesota, Minneapolis

Kia Bazargan, University of Minnesota, Minneapolis

pp. 300

Real-time Extensions to a C-like Hardware Description Language (Abstract)

Tim Todman, Imperial College

Wayne Luk, Imperial College

pp. 302

PDF

RSA encryption using Extended Modular Arithmetic on the Quicksilver COSM Adaptive Computing Machine (PDF)

Kiran Puttegowda, Virginia Tech

Peter Athanas, Virginia Tech

pp. 305

Kernel Formation in Garpcc (PDF)

Tim Callahan

pp. 308

Author Index (PDF)

pp. 311