CSDL - Proceedings F

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Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems (Abstract)

Sze-Wei Ong, University of Tennessee

Nabil Kerkiz, University of Tennessee

Bernadeta Srijanto, University of Tennessee

Chandra Tan, University of Tennessee

Mike Langston, University of Tennessee

Danny Newport, University of Tennessee

Don Bouldin, University of Tennessee

pp. 10-20

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Parameterized Module Generator for an FPGA-Based Electronic Cochlea (Abstract)

M. P. Leong, Chinese University of Hong Kong

C. T. Jin, University of Sydney

P. H. W. Leong, Chinese University of Hong Kong

pp. 21-30

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Session 2: Tools

Novel Algorithm Combining Temporal Partitioning and Sharing of Functional Units (Abstract)

Jo?o M. P. Cardoso, University of Algarve

pp. 31-40

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Instrumenting Bitstreams for Debugging FPGA Circuits (Abstract)

Paul Graham, Brigham Young University

Brent Nelson, Brigham Young University

Brad Hutchings, Brigham Young University

pp. 41-50

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Session 3: Arithmetic

The Multiple Wordlength Paradigm (Abstract)

George A. Constantinides, Imperial College

Peter Y.K. Cheung, Imperial College

Wayne Luk, Imperial College

pp. 51-60

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FPGA Implementation of Pipelined On-Line Scheme for 3-D Vector Normalization (Abstract)

Zhijun Huang, University of California at Los Angeles

Miloš D. Ercegovac, University of California at Los Angeles

pp. 61-70

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A Reconfigurable Co-Processor for Variable Long Precision Arithmetic Using Indian Algorithms (Abstract)

Ranjani Parthasarathi, Anna University

Easwaran Raman, Anna University

Karthik Sankaranarayanan, Anna University

Lakshmi N Chakrapani, Anna University

pp. 71-80

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Session 4: JBits

An Efficient Content-Addressable Memory Implementation Using Dynamic Routing (Abstract)

Philip B. James-Roxby, Xilinx, Inc.

Daniel J. Downs, Xilinx, Inc.

pp. 81-90

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Lava and JBits: From HDL to Bitstream in Seconds (Abstract)

Satnam Singh, Xilinx Inc.

Phil James-Roxby, Xilinx Inc.

pp. 91-100

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Session 5: Architecture I

Architecture and Application of PLATO, A Reconfigurable Active Network Platform (Abstract)

Apostolos Dollas, Technical University of Crete

Dionisios Pnevmatikatos, Technical University of Crete

Nikolaos Aslanides, Technical University of Crete

Stamatios Kavvadias, Technical University of Crete

Euripides Sotiriades, Technical University of Crete

Sotirios Zogopoulos, Technical University of Crete

Kyprianos Papademetriou, Technical University of Crete

Nikolaos Chrysos, Institute of Computer Science (ICS) - FORTH

Konstantinos Harteros, Institute of Computer Science (ICS) - FORTH

Emanouil Antonidakis, Technological and Educational Institute of Crete

Nikolaos Petrakis, Technological and Educational Institute of Crete

pp. 101-110

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Totem: Custom Reconfigurable Array Generation (Abstract)

Katherine Compton, Northwestern University

Scott Hauck, University of Washington

pp. 111-119

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A Cellular Automata System with FPGA (Abstract)

Tomoyoshi Kobori, University of Tsukuba

Tsutomu Maruyama, University of Tsukuba

Tsutomu Hoshino, University of Tsukuba

pp. 120-129

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Session 6: Fault Tolerance

A Fault-Tolerance Scheme for a MIN-Based Multi-Sensor System (Abstract)

Monica Alderighi, Istituto di Fisica Cosmica "G. Occhialini", CNR

Fabio Casini, Universita? di Milano

Sergio D'Angelo, Istituto di Fisica Cosmica "G. Occhialini", CNR

Davide Salvi, Istituto di Fisica Cosmica "G. Occhialini", CNR

Giacomo R. Sechi, Istituto di Fisica Cosmica "G. Occhialini", CNR

pp. 130-136

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Column-Based Precompiled Configuration Techniques for FPGA (Abstract)

Wei-Je Huang, Stanford University

Edward J. McCluskey, Stanford University

pp. 137-146

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Session 7: Architecture II

Configuration Compression for Virtex FPGAs (Abstract)

Zhiyuan Li, Northwestern University

Scott Hauck, University of Washington

pp. 147-159

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An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia (Abstract)

Mihai Sima, Delft University of Technology and Philips Research

Sorin Cotofana, Delft University of Technology

Jos T. J. van Eijndhoven, Philips Research

Stamatis Vassiliadis, Delft University of Technology

Kees Vissers, TriMedia Technologies, Inc.

pp. 160-169

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Pilchard — A Reconfigurable Computing Platform with Memory Slot Interface (Abstract)

P. H. W. Leong, Chinese University of Hong Kong

M. P. Leong, Chinese University of Hong Kong

O. Y. H. Cheung, Chinese University of Hong Kong

T. Tung, Chinese University of Hong Kong

C. M. Kwok, Chinese University of Hong Kong

M. Y. Wong, Chinese University of Hong Kong

K. H. Lee, Chinese University of Hong Kong

pp. 170-179

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Session 8: Applications I

Acceleration of a 2D-FFT on an Adaptable Computing Cluster (Abstract)

Keith D. Underwood, Clemson University

Ron R. Sass, Clemson University

Walter B. Ligon, III, Clemson University

pp. 180-189

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Design and Implementation of a Generic 2-D Biorthogonal Discrete Wavelet Transform on an FPGA (Abstract)

A. Benkrid, The Queen?s University of Belfast

D. Crookes, The Queen?s University of Belfast

K. Benkrid, The Queen?s University of Belfast

pp. 190-198

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Session 9: Image Processing

An Application-Specific Compiler for High-Speed Binary Image Morphology (Abstract)

Scott Hemmert, Brigham Young University

Brad Hutchings, Brigham Young University

Anshul Malvi, Brigham Young University

pp. 199-208

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One-Step Compilation of Image Processing Applications to FPGAs (Abstract)

A. P. W. Böhm, Colorado State University

B. Draper, Colorado State University

W. Najjar, Colorado State University

J. Hammes, Colorado State University

R. Rinker, Colorado State University

M. Chawathe, Colorado State University

C. Ross, Colorado State University

pp. 209-218

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High Level Programming for FPGA Based Image and Video Processing Using Hardware Skeletons (Abstract)

K. Benkrid, The Queen?s University of Belfast

D. Crookes, The Queen?s University of Belfast

J. Smith, VisiCom division of Titan Corp.

A. Benkrid, The Queen?s University of Belfast

pp. 219-226

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Session 10: Applications II

Fast Regular Expression Matching Using FPGAs (Abstract)

Reetinder Sidhu, University of Southern California

Viktor K. Prasanna, University of Southern California

pp. 227-238

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A Configurable Hardware/Software Approach to SAT Solving (Abstract)

J. T. de Sousa, Technical University of Lisbon

J. M. da Silva, Technical University of Lisbon

M. Abramovici, Agere Systems

pp. 239-248

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Posters

The Development of an Operating System for Reconfigurable Computing (PDF)

Grant Wigley, University of South Australia

David Kearney, University of South Australia

pp. 249-250

JBits™ Design Abstractions (PDF)

Cameron Patterson, Xilinx, Inc.

Steven A. Guccione, Xilinx, Inc.

pp. 251-252

A Behavioral Synthesis Estimation Interface for Configurable Computing (PDF)

Pedro Diniz, University of Southern California

Ashok Venkatachar, University of Southern California

pp. 253-254

An Approach for Automatic Data Allocation in C to HDL Compilers (PDF)

Tsutomu Maruyama, University of Tsukuba

pp. 255-256

System on a FPGA Virtual Concatenation (PDF)

Sakir Sezer, The Queen?s University of Belfast

Eimear Stewart, The Queen?s University of Belfast

Marc Carson, Nortel Networks

Claire Greenwood, Nortel Networks

pp. 257-258

Secure Configuration of a Field Programmable Gate Array (PDF)

Tom Kean, Algotronix Ltd.

pp. 259-260

Circlets: Circuitry over the Internet (PDF)

Gordon Brebner, University of Edinburgh

Irwin Kennedy, University of Edinburgh

pp. 261-262

Evaluation of Reconfigurable Cache Module Architecture (Abstract)

Abhishek Singhal, Iowa State University

Arun Somani, Iowa State University

Akhilesh Tyagi, Iowa State University

pp. 263-266

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An External Memory Interface for FPGA-Based Computing Engines (PDF)

Joonseok Park, University of Southern California

Pedro Diniz, University of Southern California

pp. 267-268

A SW/HW Interface API for Java/FPGA Co-Designed Applets (PDF)

Yajun Ha, IMEC and K. U. Leuven

Patrick Schaumont, IMEC

Serge Vernalde, IMEC

Marc Engels, IMEC

Rudy Lauwereins, K. U. Leuven

Hugo De Man, IMEC and K. U. Leuven

pp. 269-270

The FPGA Development System CHDL (PDF)

K. Kornmesser, Universität Mannheim

A. Kugel, Universität Mannheim

R. Männer, Universität Mannheim

pp. 271-272

Combining Instruction and Loop Level Parallelism for FPGAs (Abstract)

S. Derrien, IRISA

S. Rajopadhye, IRISA

S. Sur-Kolay, ISI Calcutta

pp. 273-282

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Mutable Functional Units: Initial Results (PDF)

Yan Solihin, University of Illinois at Urbana-Champaign

Kirk W. Cameron, Florida Institute of Technology

Yong Luo, Intel Corporation

Dominique Lavenier, IRISA/CNRS

Maya Gokhale, Los Alamos National Laboratory

pp. 283-284

Rapid Synthesis of Pattern Classification Circuits (PDF)

Kenneth Mackenzie, Georgia Institute of Technology

Adam Johnson, Georgia Institute of Technology

pp. 285-286

The Effect of FPGA Granularity on Video Codec Implementations (PDF)

J? Gause, Imperial College

Carsten Reuter, University of Hannover

Holger Kropp, University of Hannover

Peter Y. K. Cheung, Imperial College

Wayne Luk, Imperial College

pp. 287-288

Accelerating Statistical Texture Analysis with an FPGA-DSP Hybrid Architecture (PDF)

F. Ibarra Pic?, Universidad de Alicante

S. Cuenca Asensi, Universidad de Alicante

V. C?rcoles, Universidad de Alicante

pp. 289-290

Hardware Implementation of Automated Sensor Self-Validation System for Cupola Furnaces (Abstract)

Wagdy H. Mahmoud, Tennessee Technological University

Roger L. Haggard, Tennessee Technological University

Mohamed Abdelrahman, Tennessee Technological University

pp. 291-299

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Reconfigurable Designs for Ray Tracing (PDF)

Tim Todman, Imperial College

Wayne Luk, Imperial College

pp. 300-301

Manufacturing Shop-Floor Supercomputer for Distributed Simulation and Control (PDF)

J. Patel, Penn State University

V. Prabhu, Penn State University

pp. 302-303

Pipelined Function Evaluation on FPGAs (Abstract)

Nicolas Boullis, Ecole Normale Superieure de Lyon

Oskar Mencer, Lucent, Bell Labs

Wayne Luk, Imperial College

Henry Styles, Imperial College

pp. 304-306

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Optimization of Logic Use on Stereo Vision Algorithm Example (PDF)

Pawel J. Rajda, AGH Technical University

pp. 307-308