CSDL - Proceedings F

Session 1: Architecture, Chair: André DeHon

Design of a VLIW Compute Accelerator on the Transmogrifier-2 (Abstract)

L. Louis Zhang, University of Toronto

Qiang Wang, University of Toronto

David M. Lewis, University of Toronto

pp. 3

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A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems (Abstract)

Mark J. Boyd, University of California at Santa Cruz

Tracy Larrabee, University of California at Santa Cruz

pp. 13

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Configuration Caching Management Techniques for Reconfigurable Computing (Abstract)

Zhiyuan Li, Northwestern University

Katherine Compton, Northwestern University

Scott Hauck, University of Washington

pp. 22

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Session 2: Compilation 1, Chair: Wayne Luk

A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems (Abstract)

P. Banerjee, Northwestern University

N. Shenoy, Northwestern University

A. Choudhary, Northwestern University

S. Hauck, Northwestern University

C. Bachmann, Northwestern University

M. Haldar, Northwestern University

P. Joisha, Northwestern University

A. Jones, Northwestern University

A. Kanhare, Northwestern University

A. Nayak, Northwestern University

S. Periyacheri, Northwestern University

M. Walkden, Northwestern University

D. Zaretsky, Northwestern University

pp. 39

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Stream-Oriented FPGA Computing in the Streams-C High Level Language (Abstract)

Maya B. Gokhale, Los Alamos National Laboratory

Janice M. Stone, Los Alamos National Laboratory

Jeff Arnold, Adaptive Silicon, Inc.

Mirek Kalinowski, Sarnoff Corporation

pp. 49

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Session 3: Applications 1, Chair: Philip Freiden

A Reconfigurable Computing Architecture for Microsensors (Abstract)

Stephen Scalera, Sanders, a Lockheed Martin Company

Mark Falco, Sanders, a Lockheed Martin Company

Brent Nelson, Brigham Young University

pp. 59

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FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor (Abstract)

K.H. Leung, Chinese University of Hong Kong

K.W. Ma, Chinese University of Hong Kong

W.K. Wong, Chinese University of Hong Kong

P.H.W. Leong, Chinese University of Hong Kong

pp. 68

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Customizing Graphics Applications: Techniques and Programming Interface (Abstract)

Henry Styles, Imperial College

Wayne Luk, Imperial College

pp. 77

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Session 4: Compilation 2, Chair: Scott Hauck

Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines (Abstract)

Pedro Diniz, University of Southern California

Joonseok Park, University of Southern California

pp. 91

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A C to HDL Compiler for Pipeline Processing on FPGAs (Abstract)

Tsutomu Maruyama, University of Tsukuba

Tsutomu Hoshino, University of Tsukuba

pp. 101

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Session 5: Cryptographic Applications, Chair: John McHenry

High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm) (Abstract)

Cameron Patterson, Xilinx, Inc.

pp. 113

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A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA (Abstract)

M.P. Leong, Chinese University of Hong Kong

O.Y.H. Cheung, Chinese University of Hong Kong

K.H. Tsoi, Chinese University of Hong Kong

P.H.W. Leong, Chinese University of Hong Kong

pp. 122

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An Adaptive Cryptographic Engine for IPSec Architectures (Abstract)

Andreas Dandalis, University of Southern California

Viktor K. Prasanna, University of Southern California

Jose D. P. Rolim, University of Southern California

pp. 132

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Session 6: Programming Tools, Chair: Brad Hutchings

Death of the RLOC? (Abstract)

Satnam Singh, Xilinx Inc.

pp. 145

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Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations (Abstract)

Philip James-Roxby, University of Birmingham

Steven A. Guccione, Xilinx Incorporated

pp. 153

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Session 7: Fault Tolerance, Chair: Philip Kuekes

Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration (Abstract)

John Emmert, University of Kentucky

Charles Stroud, University of Kentucky

Brandon Skaggs, University of Kentucky

Miron Abramovici, Bell Labs - Lucent Technologies

pp. 165

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An ACS Robotic Control Algorithm with Fault Tolerant Capabilities (Abstract)

Shu-Yi Yu, Stanford University

Nirmal Saxena, Stanford University

Edward J. McCluskey, Stanford University

pp. 175

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Tunable Fault Tolerance for Runtime Reconfigurable Architectures (Abstract)

Steven K. Sinha, Carnegie Mellon University

Peter M. Kamarchik, Carnegie Mellon University

Seth C. Goldstein, Carnegie Mellon University

pp. 185

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Session 8: Wireless Applications, Chair: Tom Kean

Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs (Abstract)

Chris Dick, Xilinx Inc.

Fred Harris, California State University at San Diego

Michael Rice, Brigham Young University

pp. 195

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Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems (Abstract)

Ahmad Alsolaim, Ohio University

Janusz Starzyk, Ohio University

Jürgen Becker, Darmstadt University of Technology

Manfred Glesner, Darmstadt University of Technology

pp. 205

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Session 9: Applications 2, Chair: Mike Butts

Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware (Abstract)

pp. 217

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Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine (PDF)

Euripides Sotiriades, Technical University of Crete

Apostolos Dollas, Technical University of Crete

Peter Athanas, Virginia Tech

pp. 227

An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars (Abstract)

Cristian Ciressan, Ecole Polytechnique F?d?rale de Lausanne

Eduardo Sanchez, Ecole Polytechnique F?d?rale de Lausanne

Martin Rajman, Ecole Polytechnique F?d?rale de Lausanne

Jean-Cedric Chappelier, Ecole Polytechnique F?d?rale de Lausanne

pp. 236

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Session 10: Applications 3, Chair: Don Bouldin

A Reliable LZ Data Compressor on Reconfigurable Coprocessors (Abstract)

Wei-Je Huang, Stanford University

Nirmal Saxena, Stanford University

Edward J. McCluskey, Stanford University

pp. 249

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EVIDENCE: An FPGA-Based System for Photon EVent IDENtification and CEntroiding (Abstract)

Monica Alderighi, Istituto di Fisica Cosmica ?G. Occhialini?

Sergio D'Angelo, Istituto di Fisica Cosmica ?G. Occhialini?

Giacomo R. Sechi, Istituto di Fisica Cosmica ?G. Occhialini?

pp. 259

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Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware (Abstract)

Michael J. Wirthlin, Brigham Young University

Steve Morrison, Brigham Young University

Paul Graham, Brigham Young University

Brian Bray, Sandia National Laboratories

pp. 267

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Poster Session 1

Configuration Relocation and Defragmentation for Reconfigurable Computing (Abstract)

Katherine Compton, Northwestern University

James Cooley, Northwestern University

Stephen Knol, Northwestern University

Scott Hauck, University of Washington

pp. 279

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Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW (Abstract)

T. Inuo

pp. 281

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Hardware Accelerator for Subgraph Isomorphism Problems (Abstract)

Shuichi Ichikawa, Toyohashi University of Technology

Lerdtanaseangtham Udorn, Toyohashi University of Technology

Kouji Konishi, Toyohashi University of Technology

pp. 283

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A Reconfigurable Hardware Platform for Digital Real-Time Signal Processing in Television Studios (Abstract)

pp. 285

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Reconfigurable Array Media Processor (RAMP) (Abstract)

Kamlesh Rath, University of Texas at Dallas

Sirisha Tangirala, University of Texas at Dallas

Patrick Friel, University of Texas at Dallas

Poras Balsara, University of Texas at Dallas

Jose Flores, Texas Instruments

John Wadley, Texas Instruments

pp. 287

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Internet Connected FPGAs (Abstract)

Hamish Fallside, Xilinx Inc

Michael John Sebastian Smith, University of Hawaii

pp. 289

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A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems (Abstract)

O. Yamamoto, Keio University

Yuichiro Shibata, Keio University

Hitoshi Kurosawa, Keio University

Hideharu Amano, Keio University

pp. 291

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Poster Session 2

A Virtual Hardware System on a Dynamically Reconfigurable Logic Device (Abstract)

Y. Shibata, Keio University

M. Uno, Keio University

H. Amano, Keio University

K. Furuta, NEC Corp.

T. Fujii, NEC Corp.

M. Motomura, NEC Corp.

pp. 295

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Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures (Abstract)

R. Maestre, Universidad Complutense

M. Fernandez, Universidad Complutense

R. Hermida, Universidad Complutense

F.J. Kurdahi, University of California at Irvine

N. Bagherzadeh, University of California at Irvine

H. Singh, University of California at Irvine

pp. 297

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A Communication Scheduling Algorithm for Multi-FPGA Systems (Abstract)

Jinwoo Suh, University of Southern California

Dong-In Kang, University of Southern California

Stephen P. Crago, University of Southern California

pp. 299

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Preemptive Multitasking on FPGAs (Abstract)

L. Levinson, Weizmann Institute of Science

R. Männer, University of Mannheim

M. Sessler, University of Mannheim

H. Simmler, University of Mannheim

pp. 301

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BigSky-An On-Line Arithmetic Design Tool for FPGAs (Abstract)

Aaron Schneider, University of California at Los Angeles

Robert McIlhenny, University of California at Los Angeles

M.D. Ercegovac, University of California at Los Angeles

pp. 303

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Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings (Abstract)

pp. 305

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Multiple Precision for Resource Minimization (Abstract)

George A. Constantinides, Imperial College

Peter Y.K. Cheung, Imperial College

Wayne Luk, Imperial College

pp. 307

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StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox (Abstract)

M. Morf

pp. 309

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Poster Session 3

An FPGA-Based Array Processor for an Ionospheric-Imaging Radar (Abstract)

Tim Tuan, University of Washington

Miguel Figueroa, University of Washington

Frank Lind, University of Washington

Chucai Zhou, University of Washington

Chris Diorio, University of Washington

John Sahr, University of Washington

pp. 313

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Embedded Compilation for Multimedia Applications (Abstract)

N. Daw

S. Goldstein

D. Strelow

pp. 315

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Interfacing Reconfigurable Logic with a CPU (Abstract)

pp. 317

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A Run-Time Reconfigurable Plug-In for the Winamp MP3 Player (PDF)

Jonathan Scalera, Virginia Tech

Mark Jones, Virginia Tech

pp. 319

Accelerating Embedded Applications using Dynamically Reconfigurable Hardware and Evolutionary Algorithms (Abstract)

J. Harkin, University of Ulster

T.M McGinnity, University of Ulster

L.P Maguire, University of Ulster

pp. 321

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Implementation of a Configurable Controller for an AC Drive Control: A Case Study (Abstract)

pp. 323

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Pattern Recognition and Reconstruction on an FPGA Coprocessor Board (Abstract)

pp. 325

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Poster Session 4

FCCMS and the Memory Wall (Abstract)

S. Derrien, IRISA

S. Rajopadhye, IRISA

pp. 329

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A C to Hardware/Software Compiler (Abstract)

Kiarash Bazargan, Northwestern University

Ryan Kastner, Northwestern University

Seda Ogrenci, Northwestern University

Majid Sarrafzadeh, Northwestern University

pp. 331

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Evaluating Hardware Compilation Techniques (Abstract)

Markus Weinhardt, Imperial College

Wayne Luk, Imperial College

pp. 333

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Adapting Constant Multipliers in a Neural Network Implementation (Abstract)

P. James-Roxby

B. Blodget

pp. 335

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A Networked FPGA-Based Hardware Implementation of a Neural Network Application (Abstract)

Héctor Fabio Restrepo, Swiss Federal Institute of Technology

Ralph Hoffmann, Swiss Federal Institute of Technology

Andres Perez-Uribe, Swiss Federal Institute of Technology

Christof Teuscher, Swiss Federal Institute of Technology

Eduardo Sanchez, Swiss Federal Institute of Technology

pp. 337

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Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems (Abstract)

Katsuharu Suzuki, University of California at Santa Cruz

Michael X. Wang, University of California at Santa Cruz

Zhao Fang, University of California at Santa Cruz

Wayne W.-M. Dai, University of California at Santa Cruz

pp. 339

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An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing (Abstract)

Timothy Courtney, Queen's University of Belfast

Richard Turner, Queen's University of Belfast

Roger Woods, Queen's University of Belfast

pp. 341

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Combining Serialization and Reconfiguration for Convolver Designs (Abstract)

Arran Derbyshire, Imperial College

Wayne Luk, Imperial College

pp. 344

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Author Index (PDF)

pp. 347