CSDL - Proceedings F

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Session 1: Architectures I, Chair: Scott Hauck

A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications (Abstract)

Takashi Miyamori

Kunle Olukotun

pp. 2

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Exploring Optimal Cost-Performance Designs for Raw Microprocessors (Abstract)

pp. 12

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The NAPA Adaptive Processing Architecture (Abstract)

H. Holt

pp. 28

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Session 2: Special Purpose Systems, Chair: Jeffrey Arnold

A Stream-Based Configurable Computing Radio Testbed (Abstract)

pp. 40

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Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation (Abstract)

Apostolos Dollas, Technical University of Crete

Euripides Sotiriades, Technical University of Crete

Apostolos Emmanouelides, Technical University of Crete

pp. 48

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Session 3: Architectures II, Chair: Tom Kean

New FPGA Architecture for Bit-Serial Pipeline Datapath (Abstract)

pp. 58

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Plastic Cell Architecture: Towards Reconfigurable Computing for General-Purpose (Abstract)

H. Ito

pp. 68

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The Design and Implementation of a Context Switching FPGA (Abstract)

S.M. Scalera

J.R. Vázquez

pp. 78

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Session 4: Applications I, Chair: John McHenry

A Run-Time Reconfigurable Engine for Image Interpolation (Abstract)

pp. 88

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Hardware/Software Integration in Solar Polarimetry (Abstract)

M. Shand

L. Moll

pp. 96

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Session 5: Compilers, Chair: Don Bouldin

An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems (Abstract)

pp. 106

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Specifying and Compiling Applications for RaPiD (Abstract)

pp. 116

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NAPA C: Compiling for a Hybrid RISC/FPGA Architecture (Abstract)

Maya B. Gokhale, Sarnoff Corp.

Janice M. Stone, Sarnoff Corp.

pp. 126

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Session 6: Tools for Run Time Reconfiguration, Chair: Satnam Singh

Configuration Compression for the Xilinx XC6200 FPGA (Abstract)

Scott Hauck, Northwestern University

Zhiyuan Li, Northwestern University

Eric Schwabe, Northwestern University

pp. 138

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Automating Production of Run-Time Reconfigurable Designs (Abstract)

N. Shirazi

W. Luk

P.Y.K. Cheung

pp. 147

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Session 7: Module Generation, Chair: Wayne Luk

Object Oriented Circuit-Generators in Java (Abstract)

M. Chu

pp. 158

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PAM-Blox: High Performance FPGA Design for Adaptive Computing (Abstract)

Oskar Mencer, Stanford University

Martin Morf, Stanford University

Michael J. Flynn, Stanford University

pp. 167

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JHDL - An HDL for Reconfigurable Systems (Abstract)

P. Bellows

B. Hutchings

pp. 175

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Session 8: Applications II, Chair: Peter Athanas

Accelerating Boolean Satisfiability with Configurable Hardware (Abstract)

pp. 186

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William H. Mangione-Smith

Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability (Abstract)

Azra Rashid

Jason Leonard

pp. 196

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Session 9: Arithmetic, Chair: Mike Butts

A Re-evaluation of the Practicality of Floating-Point Operations on FPGAs (Abstract)

pp. 206

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A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures (Abstract)

Alexandre F. Tenca, Oregon State University

Milos D. Ercegovac, University of California at Los Angeles

pp. 216

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A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure (Abstract)

Simon D. Haynes

Peter Y.K. Cheung

pp. 226

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Session 10: Applications III, Chair: Mark Shand

Accelerating Adobe Photoshop with the Reconfigurable Logic (Abstract)

S. Singh

R. Slous

pp. 236

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Analysis of the XC6000 Architecture for Embedded System Design (Abstract)

pp. 245

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Poster Session 1

A FPGA Based Forth Microprocessor (Abstract)

P.H.W. Leong, The Chinese University of Hong Kong

P.K. Tsang, The Chinese University of Hong Kong

T.K. Lee, The Chinese University of Hong Kong

pp. 254

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PROGRAPE-1: A Programmable Special-Purpose Computer for Many-Body Simulations (Abstract)

pp. 256

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RVC - A Reconfigurable Coprocessor for Vector Processing Applications (Abstract)

Jose C. Alves

Jose S. Matos

pp. 258

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The Systolic Array Genetic Algorithm, An Example of Systolic Arrays as a Reconfigurable Design Methodology. (Abstract)

I.M. Bland

G.M. Megson

pp. 260

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50 kHz Pattern Recognition on the Large FPGA Processor Enable++ (Abstract)

R. Lay

pp. 262

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An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration (Abstract)

Y. Yabe

pp. 264

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Mapping the MD5 Hash Algorithm onto the NAPA Architecture (Abstract)

J.M. Arnold

pp. 267

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General Purpose vs. Custom FCCM's: a Comparison of Splash2, Quickturn RPM, and GE1 for Golomb Ruler Derivation (Abstract)

Apostolos Dollas, Technical University of Crete

Euripides Sotiriades, Technical University of Crete

Apostolos Emmanouelides, Technical University of Crete

Lee House, Technical University of Crete

pp. 269

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An Architecture Simulator for National Semiconductor's Adaptive Processing Architecture (NAPA) (Abstract)

J.M. Arnold

pp. 271

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Benchmarking Technology for Configurable Computing System (Abstract)

S. Wadi

pp. 273

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Reconfigurable Processor Architectures Exploiting High Bandwidth Optical Channels (Abstract)

pp. 275

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Poster Session 2

Some Applications of FPGAs in Bio-Inspired Hardware (Abstract)

pp. 278

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A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware (Abstract)

J.C. Ferreira

J.S. Matos

pp. 280

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Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application (Abstract)

Ruth Sivilotti, Myricom, Inc.

Young Cho, Myricom, Inc.

Wen-King Su, Myricom, Inc.

Danny Cohen, Myricom, Inc.

Brian Bray, Sandia National Laboratories

pp. 282

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An FPGA Implementation of GENET for Solving Graph Coloring Problems (Abstract)

T.K. Lee, The Chinese University of Hong Kong

P.H.W. Leong, The Chinese University of Hong Kong

K.H. Lee, The Chinese University of Hong Kong

K.T. Chan, The Chinese University of Hong Kong

S.K. Hui, The Chinese University of Hong Kong

H.K. Yeung, The Chinese University of Hong Kong

M.F. Lo, The Chinese University of Hong Kong

J.H.M. Lee, The Chinese University of Hong Kong

pp. 284

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SLAAC: A Distributed Architecture for Adaptive Computing (Abstract)

pp. 286

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RENCO: A Reconfigurable Network Computer (Abstract)

pp. 288

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Hardware Implementation of Generalized Profile Search on the GENSTORM Machine (Abstract)

pp. 290

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FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for Smartcards (Abstract)

H. Ploog

D. Timmermann

pp. 292

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Characterization and Parameterization of a Pipeline Reconfigurable FPGA (Abstract)

pp. 294

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Poster Session 3

A FPGA-Based Custom Computing System for Solving the Assignment Problem (Abstract)

D.L. Hung

J. Wang

pp. 298

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Circlets: Circuits as Applets (Abstract)

Gordon Brebner, University of Edinburgh

pp. 300

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Dynamic Reconfiguration to Support Concurrent Applications (Abstract)

J. Jean

K. Tomko

V. Yavagal

R. Cook

J. Shah

pp. 302

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A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing (Abstract)

pp. 304

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Frequency-Domain Sonar Processing in FPGAs and DSPs (Abstract)

Paul Graham

Brent Nelson

pp. 306

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Dynamic Specialization of XC6200 FPGAs by Partial Evaluation (Abstract)

pp. 308

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DES Key Breaking, Encryption and Decryption on the XC6216 (Abstract)

Tom Kean, Xilinx Development Corporation

Ann Duncan, Xilinx Development Corporation

pp. 310

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An Effective Design System for Dynamically Reconfigurable Architectures (Abstract)

pp. 312

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Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures (Abstract)

A. Dandalis

V.K. Prasanna

pp. 314

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Poster Session 4

Fast Partial Reconfiguration for FCCMs (Abstract)

S Sezer

R Woods

J Heron

A Marshall

pp. 318

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Reconfigurable Hardware as Shared Resource for Parallel Threads (Abstract)

G. Haug

W. Rosenstiel

pp. 320

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Digit-Serial DSP Library for Optimized FPGA Configuration (Abstract)

Hanho Lee, University of Minnesota

Gerald E. Sobelman, University of Minnesota

pp. 322

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A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable Systems (Abstract)

pp. 324

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High Level Synthesis for Designing Custom Computing Hardware (Abstract)

pp. 326

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Karthikeya M. Gajjala Purna

Temporal Partitioning and Scheduling for Reconfigurable Computing (Abstract)

Dinesh Bhatia

pp. 329

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Implementation of RNS Addition and RNS Multiplication into FPGAs (Abstract)

Luiz Maltar, COPPE-Universidade Federal do Rio de Janeiro

Felipe M.G. França, COPPE-Universidade Federal do Rio de Janeiro

Vladimir C. Alves, COPPE-Universidade Federal do Rio de Janeiro

Cláudio L. Amorim, COPPE-Universidade Federal do Rio de Janeiro

pp. 331

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A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine (Abstract)

A. Walters

P. Athanas

pp. 333

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Reconfigurable Computing for Space-Time Adaptive Processing (Abstract)

Nikhil D. Gupta, Texas Tech University

John K. Antonio, Texas Tech University

Jack M. West, Texas Tech University

pp. 335

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Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks (Abstract)

Manoucher Shaditalab, ?cole Polytechnique de Montr?al

Guy Bois, ?cole Polytechnique de Montr?al

Mohamad Sawan, ?cole Polytechnique de Montr?al

pp. 337

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Implementing C Algorithms in Reconfigurable Hardware Using C2Verilog (Abstract)

D. Soderman

Y. Panchul

pp. 339

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Author Index (PDF)

pp. 343