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IEEE Symposium on FPGAs for Custom Computing Machines
Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks
Napa Valley, California
April 15-April 17
ISBN: 0-8186-8900-5
Manoucher Shaditalab, ?cole Polytechnique de Montr?al
Guy Bois, ?cole Polytechnique de Montr?al
Mohamad Sawan, ?cole Polytechnique de Montr?al
Design and implementation of parallel pipelined Fast Fourier Transform (FFT), using Decimation in Frequency (DIF) algorithm on FPGA's is presented. The FFT core for 1024 complex data point is implemented on the X-CIM which is a Re-configurable Acceleration Subsystem (RAS) with a TMS320C4x DSP-processor and two XC4013 FPGA as its processing units. The proposed FFT machine is an alternative to the bit serial-parallel FFT algorithm using Distributed Arithmetic Look Up Table (DALUT) method. The advantage of proposed design is mainly in its cost effective and hardware-efficient parallel implementations of the N-point DFT, offering highly attractive throughput rates in relation to the conventional DSP processors. Moreover, the processor's data-path structure is independent of sampled data-points, and it has a self-sorting property where the output is in properly ordered form. Our goal is to improve size-performance requirements of an FFT core function using modular and hierarchical VHDL description combined with IP_Core library elements from Xilinx.
Citation:
Manoucher Shaditalab, Guy Bois, Mohamad Sawan, "Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks," fccm, pp.337, IEEE Symposium on FPGAs for Custom Computing Machines, 1998
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